Rational PLL Frequency Division for Low-Spur Multi-Frequency Synthesis
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Solution Overview
Problem
Conventional fractional-N frequency synthesizers face challenges with fractional spurs due to lack of resolution in the feedback path, leading to PLL frequency jitter and limitations in resolving rational numbers, especially when using a single reference clock for multiple synthesized frequencies.
Innovation Solution
A method for low resolution rational division in frequency synthesis that uses a flexible accumulator to determine a true rational number divisor, reducing bit resolution through complementing functions when necessary, allowing for either rational or fractional division in the PLL feedback path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional fractional-N frequency synthesizers use fractional number decimal values in PLL architectures, then frequency synthesis capability is achieved, but fractional spurs are generated due to lack of resolution in the feedback path
Solution Approach 1:
The patent inverts the conventional approach by using true rational numbers (integers only) instead of fractional decimals in the feedback path. The division ratio is expressed as N/D where N and D are integers, eliminating the need for fractional representations and their associated quantization errors that cause spurs and jitter.
Solution Approach 2:
The patent changes the parameter representation from fractional decimal values to integer-based rational numbers. By modifying how the division ratio is expressed and processed (using integer numerator and denominator separately), the system achieves frequency synthesis without the harmful effects of fractional spurs.
2Measurement precision
If rational numbers with large numerator bit resolution are used to achieve precise frequency division, then frequency resolution is improved, but the number of bits required exceeds available register capacity
Solution Approach 1:
The patent segments the division ratio into two separate integer parameters: numerator N and denominator D. This segmentation allows the system to achieve high frequency resolution through the relationship between N and D without requiring a single large-bit register, thereby reducing the bit resolution requirements for individual components.
Solution Approach 2:
The patent employs dynamic adjustment of the division ratio by independently controlling the numerator and denominator integers. This dynamic approach allows the system to achieve various frequency resolutions by adjusting the relationship between N and D, rather than being constrained by fixed bit-width registers.
3Adaptability or versatility
If a single reference clock is used to generate multiple synthesized frequencies, then system simplicity and adaptability are improved, but resolving rational numbers requires more bits than available in the feedback path
Solution Approach 1:
The patent creates a universal frequency synthesis approach where a single reference clock can generate multiple synthesized frequencies by dynamically adjusting the integer numerator and denominator. This multi-functional capability allows the same hardware to achieve various frequency divisions without requiring additional reference clocks or complex fractional arithmetic units.
Solution Approach 2:
Instead of trying to fit fractional numbers into limited-bit registers (which causes truncation and loss of information), the patent inverts the approach by using integer-only arithmetic with separate numerator and denominator. This inversion eliminates the information loss problem while maintaining the ability to generate multiple frequencies from a single reference.
Data Source
AI summary
A method is provided for synthesizing signal frequencies using low resolution rational division. A reference frequency value and synthesized frequency value are accepted. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (n) and an integer value denominator (d) are determined, with n/d=I(N/D)=I+N/D=(I+1)−(D−N)/D), and where N/D<1. An accumulator creates a sum of (D−N) and a count from a previous cycle, and creates a difference between the sum and the denominator. The sum is compared with the denominator, and a first carry bit is generated. The complement of the first carry bit is added to a first binary sequence, and the first binary sequence is used to generate a k-bit quotient. The k-bit quotient is subtracted from (I+1) to generate a divisor.