Ray-Box Intersection Circuitry With Cached Slopes and Fewer Multipliers
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Solution Overview
Problem
Ray tracing in graphics processors is computationally expensive due to the need for numerous floating-point multipliers in traditional ray-box intersection tests, which increases processor area and power consumption, especially in wide-branching BVHs and parallel hardware accelerators.
Innovation Solution
Implementing a ray cache that stores pre-computed information such as transformed slopes and low-precision reciprocals, and using interval arithmetic with reduced floating-point multipliers for box intersection tests, reducing the number of multipliers required from six to four per test.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional ray-box intersection tests are used, then accurate intersection results are obtained, but the number of floating-point multipliers increases, leading to larger processor area and higher power consumption
Solution Approach 1:
The patent applies preliminary action by pre-computing transformed slopes and low-precision reciprocals of ray direction components before the actual intersection test. These pre-computed values are stored in a ray cache, allowing the intersection test to use simpler arithmetic operations with reduced precision, thereby reducing the number of floating-point multipliers from six to four per test while maintaining accurate intersection results
Solution Approach 2:
The patent changes the precision parameters of the computation by using low-precision reciprocals and transformed slopes instead of full-precision floating-point values. This parameter change allows the intersection test to achieve the same accuracy with fewer floating-point multipliers, directly resolving the contradiction between measurement precision and device complexity
2Measurement precision
If traditional ray-box intersection tests are used, then accurate intersection results are obtained, but processor area and power consumption increase
Solution Approach 1:
By pre-computing and caching transformed slopes and reciprocals, the patent reduces the number of floating-point multipliers required during the actual intersection test. Since floating-point multiplication is energy-intensive, reducing their count from six to four per test directly lowers power consumption while maintaining intersection accuracy through the use of pre-computed low-precision values
3Measurement precision
If traditional ray-box intersection tests are used, then accurate intersection results are obtained, but circuit area increases
Solution Approach 1:
The patent reduces circuit area by pre-computing and storing transformed slopes and reciprocals in a ray cache. This preliminary action allows the intersection test circuit to use simpler arithmetic operations with fewer floating-point multipliers (reduced from six to four per test), thereby reducing the overall processor area required while maintaining intersection accuracy through low-precision arithmetic
Data Source
AI summary
Techniques are disclosed relating to ray intersection tests for ray tracing in graphics processors. In some embodiments, a ray cache stores, transformed ray direction corresponding to a transform of a ray based on its dominant direction axis. Ray intersect acceleration circuitry may determine whether a ray intersects a bounding volume of a bounding volume hierarchy (BVH) data structure. Ray-plane test circuitry may perform a set of six ray-plane tests for the bounding volume using at most four floating-point multiplication operations by four multiplier circuits. The floating-point operations may operate on the transformed ray direction components from the ray cache circuitry and coordinate information for the bounding volume. Disclosed techniques may reduce area and power consumption by avoiding multiplier circuitry for some ray-plane tests.