Ray Tracing Pipeline Stack Throttling for BVH Traversal Load

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Solution Overview

Problem

Ray tracing is resource-intensive and inefficient for real-time performance due to the computational demands of visibility queries and ray-scene intersections, particularly in processing ray-scene intersections using bounding volume hierarchies (BVHs).

Innovation Solution

Implementing a hybrid approach that combines ray tracing with rasterization techniques, utilizing dedicated ray tracing cores for BVH traversal and intersection operations, while freeing up general-purpose graphics processing units for other tasks, and incorporating machine learning for denoising and optimization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If ray tracing is used for real-time rendering, then image quality and realism are improved, but computational resource consumption increases significantly

Engineering Contradiction:
Improveimage qualityVSAvoidcomputational resource consumption
Core Design Contradiction:
Manufacturing precisionVSUse of energy by moving object

Solution Approach 1:

The patent segments the rendering pipeline into two distinct paths: a rasterization pipeline for general graphics processing and a ray tracing pipeline for specific lighting and shadow effects. This segmentation allows the system to apply computationally intensive ray tracing only where needed while using efficient rasterization for other rendering tasks, thereby improving image quality in critical areas without proportionally increasing overall computational resource consumption.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If ray tracing is used for real-time rendering, then visual realism is improved, but processing speed deteriorates

Engineering Contradiction:
Improvevisual realismVSAvoidprocessing speed
Core Design Contradiction:
Manufacturing precisionVSSpeed

Solution Approach 1:

The patent implements dynamic control of the ray tracing pipeline through throttling mechanisms that adjust processing based on scene complexity, frame timing, and resource availability. The system dynamically enables or disables ray tracing for specific objects or lighting scenarios, and adjusts the number of rays traced per pixel, allowing the processing speed to adapt while maintaining visual realism when conditions permit.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If general-purpose graphics processing units are used for ray tracing, then device complexity is reduced, but processing efficiency deteriorates

Engineering Contradiction:
Improvedevice complexityVSAvoidprocessing efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent designs a hybrid rendering system where general-purpose graphics processing units can operate in multiple modes: traditional rasterization mode for standard graphics processing and ray tracing mode for lighting calculations. This multi-functionality allows the same hardware to handle both rendering approaches, reducing the need for completely separate specialized hardware while maintaining processing efficiency through mode switching based on scene requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12541908B2Apparatus and method for throttling a ray tracing pipeline
Publication Date: 2026.02.03 INTEL CORP
  • US12541908B2 patent drawing
  • US12541908B2 patent drawing
  • US12541908B2 patent drawing

AI summary

Apparatus and method for stack throttling. For example, one embodiment of an apparatus comprises: execution circuitry comprising a plurality of functional units to execute a plurality of ray shaders and generate a plurality of primary rays and a corresponding plurality of ray messages; a first in first out (FIFO) buffer to queue the ray messages generated by the EUs; a cache to store one or more of the plurality of primary rays; a memory-backed stack to store a first subset of the plurality of ray messages in a corresponding plurality of entries; memory-backed stack management circuitry to either store a second subset of the plurality of ray messages to the memory-backed stack, or to temporarily store the one or more the second subset of the plurality of ray messages to a memory subsystem based, at least in part, on a number of entries currently occupied by ray messages in the memory-backed stack; and ray traversal circuitry to read a next ray message from the memory-backed stack, retrieve a next primary ray identified by the ray message from the cache or a memory subsystem, and perform traversal operations on the next primary ray.