Ray Tracing Circuit Scheduling to Reduce Memory Access Latency
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Solution Overview
Problem
Existing graphics processing systems face inefficiencies in performing ray tracing operations, particularly in terms of memory access conflicts and latency during ray tracing acceleration data structure traversal and intersection testing.
Innovation Solution
A graphics processor with a dedicated ray tracing circuit and local storage for ray tracing acceleration data structure nodes, allowing parallel testing of rays against nodes and reducing memory access conflicts, thereby enhancing throughput and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If ray tracing acceleration data structure traversal and intersection testing are performed using shared memory resources, then device complexity is reduced, but memory access conflicts and latency increase
Solution Approach 1:
The patent divides the memory resources into separate dedicated components: a ray tracing acceleration data structure memory specifically for storing acceleration data structures, and a separate memory for storing ray tracing results. This segmentation eliminates memory access conflicts between different data structures and operations, directly resolving the contradiction between simplified device structure and reduced memory access latency.
2Productivity
If ray tracing operations are performed with multiple rays and nodes simultaneously, then productivity increases, but memory access conflicts increase
Solution Approach 1:
The patent introduces dedicated intermediate storage structures: a ray tracing acceleration data structure memory that serves as an intermediary between the ray tracing logic and the main memory system. This dedicated memory acts as a buffer that allows multiple rays and nodes to be processed simultaneously without conflicting for access to the same memory resources, thereby enabling high throughput while eliminating memory access conflicts.
Data Source
AI summary
A graphics processor operable to render frames that represent a view of a scene using a ray tracing process includes a ray tracing circuit operable to test rays against a ray tracing acceleration data structure for a ray tracing process. The ray tracing circuit comprises a ray testing circuit operable to perform ray intersection tests for nodes of a ray tracing acceleration data structure and storage local to the ray testing circuit for storing data representative of one or more nodes of a ray tracing acceleration data structure for use by the ray testing circuit. Rays for testing by the ray testing circuit are selected from a pool of one or more rays to be tested based on an indication of the ray tracing acceleration data structure node or nodes that have been stored in the local storage of the ray testing circuit.