Ray Tracing Visibility Masks for Faster Triangle Intersection Tests

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Solution Overview

Problem

Existing ray tracing technologies face challenges in achieving real-time interactive performance due to the computational intensity of testing rays against complex 3D scenes, particularly in determining visibility and handling transparent or translucent objects, which leads to performance loss and resource inefficiencies.

Innovation Solution

Implementing a ray tracing coprocessor with a visibility mask (VM) that allows for inline visibility tests within the coprocessor, reducing the need for processor intervention by using barycentric coordinates to index micro-triangles and determine visibility status directly, thereby accelerating ray-primitive intersection tests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional ray tracing methods are used to test rays against complex 3D scenes, then visibility determination can be achieved, but computational intensity increases and real-time interactive performance cannot be achieved

Engineering Contradiction:
Improvevisibility determination accuracyVSAvoidray tracing speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent segments the geometry processing by dividing scenes into micro-meshes with hierarchical structures (BVH). This segmentation allows the ray tracing system to process only relevant portions of geometry rather than testing against all primitives, significantly reducing computational intensity while maintaining visibility determination accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-processing geometry into micro-meshes and building bounding volume hierarchies before ray tracing operations. This pre-organization of geometry data enables faster runtime queries and reduces the computational burden during actual ray-primitive intersection tests, enabling real-time performance.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If processor intervention is used for visibility tests, then accuracy can be maintained, but resource inefficiencies and performance loss occur

Engineering Contradiction:
Improvevisibility test accuracyVSAvoidprocessor resource consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent implements self-service by enabling the ray tracing coprocessor to perform visibility tests autonomously using pre-computed micro-mesh data and bounding volume hierarchies. The coprocessor can determine visibility status without requiring processor intervention, reducing CPU/GPU resource consumption while maintaining test accuracy through hardware-accelerated operations.

Inventive Principle:
Principle #25Self-service

3Manufacturing precision

If traditional ray tracing handles transparent and translucent objects, then rendering accuracy is achieved, but thread divergence increases and efficiency decreases

Engineering Contradiction:
Improverendering accuracyVSAvoidthread divergence
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by using visibility masks that store per-micro-triangle transparency information. This allows the ray tracing system to handle transparent and translucent objects with localized precision rather than requiring complex thread divergence logic, as the coprocessor can directly query visibility mask data to determine how to handle each intersection independently and efficiently.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20260030832A1Accelerating triangle visibility tests for real-time ray tracing
Publication Date: 2026.01.29 NVIDIA CORP
  • US20260030832A1 patent drawing
  • US20260030832A1 patent drawing
  • US20260030832A1 patent drawing

AI summary

Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced round-trip communications with a processor are disclosed. The reduction of round-trip communications with a processor during traversal is achieved by having a visibility mask that defines visibility states for regions within a geometric primitive available to be accessed in the ray tracing hardware accelerator when a ray intersection is detected for the geometric primitive.