RC-Triggered Bracing Circuit for Low-Leakage ESD Protection
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Solution Overview
Problem
State-of-the-art ESD protection for low-voltage circuits, such as railclamps, suffer from significant standby leakage, while alternative solutions like GGNMOS transistors and LVTSCRs operate at higher clamp voltages, risking damage to the protected circuit due to increased voltage stress.
Innovation Solution
A bracing circuit with an RC input stage, a driver transistor, a series transistor acting as a high impedance element, and a mini-clamp that shorts the input line to ground during an ESD event, using a low-leakage ESD protection circuit with a grounded gate NMOS transistor to sink ESD pad current and minimize voltage stress on the protected circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a railclamp is used for ESD protection, then ESD protection is provided, but standby leakage current increases significantly
Solution Approach 1:
The ESD protection function is divided into two separate circuits: a GGNMOS transistor for sinking ESD current and a bracing circuit for voltage clamping. This segmentation allows each circuit to be optimized for its specific function, enabling low standby leakage while maintaining effective ESD protection.
Solution Approach 2:
The bracing circuit acts as an intermediary between the GGNMOS transistor and the protected circuit. It clamps the voltage to a safe level during ESD events, preventing the high voltage stress that would otherwise damage the protected circuit while allowing the GGNMOS to handle the current sinking function.
2Loss of energy
If a GGNMOS transistor is used for ESD protection, then standby leakage current is reduced, but clamp voltage increases causing voltage stress on protected circuit
Solution Approach 1:
The bracing circuit serves as a voltage clamping intermediary that limits the maximum voltage reaching the protected circuit. During ESD events, it activates to clamp the voltage to a safe level, protecting the sensitive circuit from the high voltage stress inherent in GGNMOS-based protection schemes.
Solution Approach 2:
The bracing circuit is designed to activate beforehand or simultaneously with the GGNMOS transistor during an ESD event, providing prior cushioning by establishing a voltage clamp before the full ESD current flows through the protected circuit, thereby preventing voltage damage.
3Area of moving object
If a GGNMOS transistor is used, then device width is reduced, but clamp voltage during ESD pulse increases
Solution Approach 1:
The protection function is segmented between the GGNMOS transistor (current sinking) and the bracing circuit (voltage clamping). This allows the GGNMOS to have a small device width for low leakage while the bracing circuit handles the voltage clamping function that would otherwise require a larger device.
Solution Approach 2:
The bracing circuit acts as a voltage clamp intermediary that limits the maximum voltage during ESD events, allowing the use of a small-width GGNMOS transistor without exposing the protected circuit to excessive voltage stress.
Data Source
AI summary
A protection circuit including a low-leakage electrostatic discharge (ESD) protection circuit and at least one bracing circuit, the at least one bracing circuit including an RC input stage connected between a pad and ground, a driver transistor configured to drive a plurality of components of the at least one bracing circuit, a series transistor on an input line configured to act as a high impedance element during an ESD event, and a mini-clamp configured to short the input line to ground to protect a circuit to be protected during an ESD event.