RC Time Constant Calibration Circuit Against Parasitic Capacitance
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Solution Overview
Problem
Existing RC time constant calibration methods in sigma-delta ADCs suffer from inaccuracies due to parasitic elements, especially at high clock frequencies, where small parasitic capacitances can lead to significant errors, making it challenging to achieve the required precision of +/-5% for RC time constant calibration.
Innovation Solution
A time constant calibration circuit with variable resistor and capacitor, utilizing a reference current source and comparator to iteratively adjust the resistance and capacitance values through multiple calibration cycles, minimizing the impact of parasitic capacitances and achieving calibration in a reduced number of phases, and incorporating a digital logic system to control the adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional RC time constant calibration methods are used, then calibration can be performed, but measurement precision deteriorates due to parasitic capacitances causing errors of up to 10%
Solution Approach 1:
The patent extracts and eliminates the harmful effect of parasitic capacitances by using a differential measurement approach. The calibration circuit measures the difference between two charging times (one with the capacitor under test and one without), which cancels out the parasitic capacitance component, thereby achieving high-precision calibration independent of parasitic effects.
Solution Approach 2:
The patent introduces a reference capacitor as an intermediary element in the calibration circuit. By comparing the charging time of the unknown capacitor against the reference capacitor in a differential manner, the circuit achieves accurate measurement that is immune to parasitic capacitances, as the intermediary reference element experiences the same parasitic effects.
2Measurement precision
If multiple calibration cycles with iterative adjustments are implemented, then calibration precision improves to +/-5%, but calibration time increases
Solution Approach 1:
The patent performs preliminary action by pre-charging the capacitor to a known reference voltage level before the actual measurement. This preliminary charging step establishes a consistent starting point that reduces the number of iterative adjustments needed, thereby achieving the required +/-5% precision faster and reducing overall calibration time.
3Speed
If high clock frequencies (GHz range) are used in sigma-delta ADCs, then conversion speed improves, but RC time constant precision deteriorates because small parasitic capacitances become significant relative to the small capacitance values
Solution Approach 1:
The patent implements feedback by using the measured charging time information to iteratively adjust the capacitor value and achieve the target RC time constant. The differential measurement provides accurate feedback that is independent of parasitic capacitances, enabling precise calibration even at high clock frequencies where parasitic effects would normally dominate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces calibration inaccuracies and achieves precise RC time constant calibration, independent of parasitic capacitances and comparator offsets, allowing for accurate operation of sigma-delta ADCs even at high clock frequencies.
Implementation Method 1
a capacitor having a first terminal and a second terminal... the capacitance of the capacitor is variable... through the capacitor in a second phase of the or each calibration cycle
Implementation Method 2
an amplifier having a first input, a second input and an output... the second input of the amplifier is coupleable to a reference voltage... the resistance of the resistor and/or the capacitance of the capacitor is adjusted between each calibration cycle iteratively
Data Source
Figure 1~3
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AI summary
A time constant calibration circuit and method. The circuit comprises a resistor (RREF), a capacitor (C), an amplifier (52), a first switch (SW1) and a second switch (SW2). The resistance of the resistor and/or the capacitance of the capacitor is variable. A first terminal of the resistor, a first terminal of the capacitor and a first input of the amplifier are coupled to a common node (55), which is coupleable to a reference current source (IREF). A second input of the amplifier is coupleable to a reference voltage (VB). An output of the amplifier is coupled to a second terminal of the resistor and a second terminal of the capacitor. The circuit can perform a calibration process comprising one or more calibration cycles in which the switches route a reference current through the resistor in a first phase and through the capacitor in a second phase. The resistance and/or the capacitance is adjusted between calibration cycles.