RC-Loaded Clock Buffer Tuning for Fine-Grained Skew Control
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Solution Overview
Problem
Existing methods for correcting clock skew in integrated circuits face challenges such as area, power, and complexity penalties, as well as performance reduction, particularly when using phase-locked loops or tuning clock speeds, and adding buffers increases power consumption and chip area.
Innovation Solution
A buffer circuit with resistive-capacitive (RC) loading structures between inverter stages is used to control clock skew by varying the delay, allowing for fine-grained tuning without altering cell sizes or chip routing, thus maintaining low power consumption and footprint compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a de-skew phase-locked loop or delay-locked loop is employed to align clock phases, then clock skew correction is achieved, but area, power consumption and circuit complexity increase
Solution Approach 1:
The patent changes the delay parameter of existing buffer circuits by modifying their operating conditions (such as enabling/disabling specific buffer instances or adjusting buffer characteristics) rather than adding complex PLL/DLL circuits. This allows clock skew correction through parameter adjustment of simple buffers, avoiding the area and complexity penalties of traditional approaches.
2Reliability
If clock speed is tuned to reduce clock skew, then skew correction is achieved, but circuit performance is significantly reduced due to slower clock speeds
Solution Approach 1:
The patent applies local delay adjustment to specific clock paths by selectively enabling or disabling individual buffer circuits at different locations in the clock distribution tree. This allows targeted skew correction on a path-by-path basis without globally reducing clock speed, thereby maintaining overall circuit performance while correcting local skew issues.
3Reliability
If one or more buffers are added to a clock signal path for clock tree balancing, then clock skew is reduced, but overall power consumption and chip area increase
Solution Approach 1:
The patent implements dynamic buffer control where buffer circuits can be selectively enabled or disabled based on the specific skew correction needs of different clock paths. This dynamic configuration allows the system to use only the necessary buffering resources for each operating condition, reducing overall power consumption compared to having all buffers permanently active, while still achieving adequate skew correction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control of clock skew without increasing overall power consumption or chip area, effectively balancing clock tree delays and maintaining performance without violating setup and hold times.
Implementation Method 1
The buffer circuit includes at least first and second inverter stages and a resistive-capacitive (RC) loading structure. An output of the first inverter stage is connected to an input of the second inverter stage via the RC loading structure.
Data Source
AI summary
An apparatus for controlling clock skew in an integrated circuit (IC) includes timing circuitry operative to generate a clock signal for distribution in the IC and at least one buffer circuit operative to receive the clock signal, or a signal indicative of the clock signal, and to generate a delayed version of the clock signal as an output thereof. The buffer circuit includes at least first and second inverter stages and a resistive-capacitive (RC) loading structure. An output of the first inverter stage is connected to an input of the second inverter stage via the RC loading structure. The buffer circuit has a delay associated therewith that is selectively varied as a function of one or more adjustable characteristics of the RC loading structure. Clock skew in the IC is controlled as a function of the delay of the buffer circuit.