RC Clock Generation Circuit for Fast Stable Startup
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Solution Overview
Problem
Conventional clock generation circuits require a relatively long time to generate a stable clock signal, necessitating a solution for early-stage stable clock signal production.
Innovation Solution
A clock generation circuit comprising an AND gate, inverters, capacitors, and a resistor, where the enable signal controls the clock signal's inversion and voltage changes across capacitors and resistors to achieve a constant cycle clock signal, allowing for immediate and stable output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional capacitor charging/discharging circuit is used to generate a clock signal, then the circuit structure is simple, but a relatively long time is required for generating a stable clock signal
Solution Approach 1:
The circuit performs preliminary actions by pre-charging the first capacitor C1 through the first inverter INV1 before the main clock generation cycle begins. When the enable signal transitions to H level, the clock signal immediately rises because the capacitor is already prepared, eliminating the delay associated with gradual charging. This preliminary preparation of the capacitor state allows the clock signal to become stable immediately rather than requiring a long charging period.
2Speed
If the capacitor is charged immediately when enable signal becomes H level, then the clock signal can be generated quickly, but the voltage at the sense end may not reach the threshold potential required for stable clock output
Solution Approach 1:
The second capacitor C2 serves as an intermediary energy storage element between the first capacitor C1 and the sense end. When the first capacitor discharges, it charges the second capacitor, which then provides the necessary voltage to raise the sense end potential to the threshold level. This intermediary capacitor ensures that the voltage threshold is reliably achieved without requiring the first capacitor to charge slowly, thus maintaining both speed and reliability.
Solution Approach 2:
The circuit employs periodic action through the oscillating charging and discharging cycles of the capacitors. The first capacitor charges when the clock signal is H level and discharges when it transitions to L level, creating periodic voltage changes at the sense end. This periodic charging/discharging pattern ensures that the voltage threshold is repeatedly reached, enabling stable and continuous clock signal generation at high speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit generates a stable clock signal at an early stage with a constant cycle by efficiently managing voltage changes across capacitors and resistors, ensuring rapid and consistent output.
Implementation Method 1
a first capacitor, in which an inverted clock signal from the first inverter is supplied to one end
Implementation Method 2
a resistor, in which the clock signal from the AND gate is supplied to one end
Data Source
AI summary
The clock generation circuit outputs a clock signal with a constant cycle by repeating the following operations: when an enable signal becomes a H level, the clock signal immediately rises, and a sense end is changed to a L level via a first capacitor, then a voltage of the sense end is gradually increased via a resistor, and when the sense end reaches a predetermined potential, an output of a second inverter becomes the L level, the clock signal becomes the L level, an inverted clock signal becomes the H level, and accordingly the sense end becomes the H level; and thereafter, a current flows via the resistor so that the voltage of the sense end decreases gradually, when the sense end reaches a predetermined potential, the output of the second inverter becomes a H level, the clock signal becomes the H level, the sense end is changed to a L level via the first capacitor, then the voltage of the sense end is gradually increased via the resistor, and when the sense end reaches a predetermined potential, the output of the second inverter becomes the L level and the clock signal becomes the L level.