RC Clock Circuit Tuning with Segmented Resistors
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Solution Overview
Problem
Existing RC clock circuits face challenges in achieving a stable and precise clock period tuning range due to area inefficiency and resistance variations, resulting in a limited tuning range and increased area requirements.
Innovation Solution
The implementation of a clock circuit with first and second tuning circuitry, comprising adjustable resistances and current mirror units, allows for precise tuning and a wider tuning range, reducing the overall area required by dividing the responsibility of adjusting the clock period between coarser and finer resistance tuning steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single clock trimming resistor with adjustable resistance is used to tune the clock period, then the clock period can be adjusted to a desired target value, but the area required for the tuning circuitry becomes excessively large due to the need for numerous switches and decoders
Solution Approach 1:
The single clock trimming resistor is divided into multiple sub-resistors (first clock trimming resistor and second clock trimming resistor) with different resistance ranges. This segmentation allows each sub-resistor to cover a portion of the total tuning range, reducing the number of switches and decoders needed in each segment, thereby reducing the overall circuit area while maintaining full tuning capability.
Solution Approach 2:
The patent introduces a hierarchical tuning structure where coarse tuning is performed by one sub-resistor and fine tuning is performed by another sub-resistor. This adds a dimensional aspect to the tuning process (coarse vs. fine adjustment levels), allowing precise clock period control without requiring a single large-scale adjustable resistor with all possible switching combinations.
2Adaptability or versatility
If the resistance of the clock trimming resistor is adjusted using multiple switches and decoders, then the clock period tuning range can be extended, but the device complexity increases significantly
Solution Approach 1:
The adjustable resistance function is segmented across multiple sub-resistors, each with fewer switches and simpler decoder requirements. The first clock trimming resistor handles coarse adjustment with fewer bits of control, while the second clock trimming resistor handles fine adjustment with additional bits, collectively achieving the full tuning range with reduced individual circuit complexity.
Solution Approach 2:
The patent implements a dynamic tuning approach where different sub-resistors are activated based on the required tuning range. The circuit can selectively engage coarse tuning, fine tuning, or both together, adapting the complexity of the active circuitry to the specific tuning needs, thereby managing device complexity while maintaining full adaptability.
3Adaptability or versatility
If a large number of resistance units are connected in series to achieve wide tuning range, then the clock period can be tuned over a broad range, but the area occupied by the resistance units and associated switches increases
Solution Approach 1:
The total resistance tuning range is segmented into multiple sub-ranges, each handled by a separate clock trimming resistor. Instead of using one long series chain of resistance units with many switches, the patent uses parallel segments of resistance units in different sub-resistors, each with fewer units and switches, reducing the area while maintaining the overall tuning range capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a more area-efficient clock circuit with a significantly wider and more precise clock period tuning range, reducing the overall area by over 50% while maintaining a stable clock signal.
Implementation Method 1
The second tuning circuitry includes a plurality of current mirror units, second switches and a second decoder. Current mirror units in the plurality of current mirror units are selectable by the second switches responsive to signals generated by the second decoder based on the second parameter.
Implementation Method 2
an oscillator including an RC network that produces clock output signals... a first capacitor, a second capacitor... configured to alternately charge and discharge the first capacitor and the second capacitor
Implementation Method 3
The first tuning circuitry includes an adjustable resistance that is adjustable with a first resistance tuning step... The second tuning circuitry includes an adjustable resistance that is adjustable with a second resistance tuning step
Data Source
AI summary
A circuit generates a clock signal with a tunable clock period. The circuit comprises capacitors, first tuning circuitry and second tuning circuitry. The first tuning circuitry is configured to adjust the clock period with a first period tuning step based on a first parameter and the second tuning circuit is configured to adjust the clock period with a second period tuning step based on a second parameter. The first period tuning step is different than the second period tuning step.