RC Delay Circuit ESD Protection Using Transistor Resistance
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Solution Overview
Problem
Existing RC delay circuits for ESD protection in integrated circuits face challenges in efficiently using chip area while providing significant RC delay, as large resistance requires large chip area and substituting transistors for resistors results in small effective resistance.
Innovation Solution
An RC delay circuit employing two transistors, where one transistor's gate is coupled to the voltage supply line during an ESD event, increasing its effective resistance, and a capacitor generates a decaying exponential trigger signal, allowing for a larger RC delay without significant area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If a resistor is used in an RC delay circuit to achieve large resistance for significant delay, then the RC delay time increases, but the chip area required increases significantly
Solution Approach 1:
The patent changes the operating state of the transistor between normal operation and ESD event conditions. During normal operation, the transistor is in saturation mode with low effective resistance. During an ESD event, the transistor transitions to cutoff mode with high effective resistance, achieving large RC delay without requiring large chip area.
Solution Approach 2:
The patent uses a dynamically controllable resistance element (transistor) instead of a static resistor. The resistance value changes based on the operating condition: low resistance during normal operation to minimize voltage drop, and high resistance during ESD events to maximize delay time. This dynamic adjustment resolves the area-delay tradeoff.
2Area of stationary object
If a transistor is substituted for a resistor in an RC circuit to reduce chip area, then chip area usage improves, but the effective resistance becomes too small to create a significant delay
Solution Approach 1:
The patent exploits the ability of a transistor to change its effective resistance by changing its operating state. By controlling the gate voltage, the transistor can transition between saturation mode (low resistance) and cutoff mode (high resistance), enabling significant RC delay with minimal chip area.
Solution Approach 2:
The transistor's resistance is made dynamic rather than static. During normal operation, it maintains low resistance. During an ESD event, the gate voltage changes cause the transistor to enter cutoff mode, dramatically increasing resistance and creating the necessary delay time constant without requiring large physical dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a significant increase in RC delay time by an order of magnitude while maintaining efficient use of chip area, effectively protecting integrated circuits from electrostatic discharge.
Implementation Method 1
a capacitor generates a decaying exponential trigger signal, allowing for a larger RC delay
Implementation Method 2
a trigger signal being generated on the node relative to the voltage reference line, the trigger signal having an approximate form of a decaying exponential function with a time constant equal to a product of the capacitance of the capacitor and the effective resistance of the first transistor
Data Source
AI summary
An RC delay circuit for providing electrostatic discharge (ESD) protection is described. The circuit employs an NMOS transistor and a PMOS transistor to produce a large effective resistance using a relatively small circuit layout area.