RC Delay Circuit Resetting to Mitigate PMOS NBTI Stress
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Solution Overview
Problem
Semiconductor devices with RC delay circuits are vulnerable to negative bias temperature instability (NBTI) stress, leading to fluctuations in PMOS threshold voltage and drain current, which affects the timing of control signals in memory arrays.
Innovation Solution
Incorporating a reset signal function into the RC delay circuit using NAND gates and PMOS transistors to precharge nodes to a voltage level during stand-by mode, reducing NBTI stress by resetting each node to a high voltage level, thereby mitigating degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If RC delay circuits are used to introduce delay into control signals, then timing adjustment for memory arrays is improved, but the circuits become vulnerable to NBTI stress degradation causing threshold voltage fluctuations
Solution Approach 1:
The patent applies preliminary action by precharging the output node of the RC delay circuit to a high voltage level (VDD) before the delay operation. This is achieved through a precharge transistor that is activated during a precharge phase, setting the initial voltage state of the output node. By establishing this preliminary high voltage state, the circuit reduces the stress duration on the PMOS transistor during subsequent delay operations, thereby mitigating NBTI degradation while maintaining the required delay timing functionality.
2Productivity
If PMOS transistors are used in RC load inverters, then delay functionality is achieved, but NBTI stress causes increase in threshold voltage and decrease in drain current
Solution Approach 1:
The patent implements periodic action by alternating between precharge and delay phases in the RC delay circuit operation. During the precharge phase, the output node is charged to VDD through the precharge transistor. During the delay phase, the RC circuit performs the delay function. This periodic switching reduces the continuous stress on the PMOS transistor, allowing it to recover partially between stress periods, thereby maintaining more stable drain current and threshold voltage over time while preserving delay circuit productivity.
3Device complexity
If RC delay circuits operate without reset function, then circuit simplicity is maintained, but NBTI stress degradation accumulates over time
Solution Approach 1:
The patent applies universality by designing the RC delay circuit to perform multiple functions: delay operation, precharge, and reset. The same RC delay circuit structure that provides timing delay also incorporates precharge transistors and reset functionality. This multi-functional design allows the circuit to maintain simplicity in its core delay mechanism while adding reliability features, enabling the circuit to reset its state and reduce accumulated NBTI stress without requiring a completely separate reset circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces NBTI stress degradation across the RC delay path, ensuring reliable operation by maintaining node voltages at a stable level during stand-by modes, thus enhancing the reliability and stability of semiconductor devices.
Implementation Method 1
The RC delay circuit 100 includes a first RC load inverter 106 and a second RC load inverter 120. The first RC load inverter 106 includes a first transistor 108 and a second transistor 110 having a resistor 112 therebetween. The output (Node A) of the first RC load inverter 106 is also coupled to a capacitor 114 that, with resistor 112 provides an RC time constant for the output signal on Node A.
Implementation Method 2
The first RC load inverter 106 includes a first transistor 108 and a second transistor 110 having a resistor 112 therebetween. The output (Node A) of the first RC load inverter 106 is also coupled to a capacitor 114 that, with resistor 112 provides an RC time constant for the output signal on Node A.
Data Source
AI summary
Methods and apparatus for generating a delayed output signal from an input signal applied to an RC delay circuit of a semiconductor device during an active mode. The RC delay circuit is configured to pull up a voltage level on a node responsive to a reset signal during a stand-by mode.