Reverse-conducting Power Semiconductor Device Buffer Layer
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Solution Overview
Problem
In high voltage reverse conducting gate commutated thyristor (RC-GCT) devices, the small separation distance between GCT and diode cells can lead to punch through effects and high gate-cathode leakage currents due to low doped N-drift layers, compromising blocking capability and area utilization.
Innovation Solution
The introduction of a diode buffer layer with a higher doping concentration and thickness, which reduces lateral and vertical PNP gain at the separation region, allowing for minimized separation region width while maintaining blocking capability and enhancing plasma distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the separation distance between GCT and diode cells is minimized for area utilization, then wafer area utilization is improved, but punch through effects occur and blocking capability deteriorates
Solution Approach 1:
The patent applies local quality by creating a separation region with distinct doping characteristics (higher doping concentration in the drift layer) localized between GCT and diode cells. This localized modification of doping concentration provides enhanced blocking capability specifically where needed, while maintaining minimal separation distance for area utilization.
Solution Approach 2:
The patent changes the doping concentration parameter in the drift layer of the separation region to a higher value compared to the main drift layer. This parameter change increases the electric field tolerance and prevents punch through effects, enabling minimal separation distance without compromising blocking capability.
2Area of stationary object
If the separation distance between GCT and diode cells is minimized, then area utilization is improved, but gate-cathode leakage current increases
Solution Approach 1:
The patent introduces a separation region with higher doping concentration localized between GCT and diode cells. This local modification creates a potential barrier that reduces lateral PNP gain and suppresses gate-cathode leakage current, while maintaining minimal separation distance for optimal area utilization.
Solution Approach 2:
The separation region acts as an intermediary structure between GCT and diode cells. By introducing this intermediate layer with modified doping characteristics, the patent reduces the harmful lateral PNP gain effect and gate-cathode leakage current while maintaining compact device structure.
3Object-generated harmful factors
If the doping concentration in the drift layer is increased to reduce leakage current, then gate-cathode leakage current is reduced, but plasma spreading capability deteriorates
Solution Approach 1:
The patent applies local quality by restricting the higher doping concentration to only the separation region between GCT and diode cells, while maintaining lower doping concentration in the main drift layer. This localized approach reduces leakage current where needed without impeding plasma spreading in the main conduction paths.
Solution Approach 2:
The patent segments the drift layer into two regions with different doping concentrations: a separation region with higher doping to reduce leakage, and main drift regions with lower doping to facilitate plasma spreading. This segmentation allows each region to optimize its function independently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces gate-cathode leakage current by a factor of 3 and improves on-state performance in GCT mode, while maintaining blocking capability and optimizing wafer area utilization.
Implementation Method 1
The introduction of a diode buffer layer with a higher doping concentration and thickness, which reduces lateral and vertical PNP gain at the separation region
Implementation Method 2
The separation regions 35 must be designed to enable the required blocking capability for the gate drive (gate-cathode blocking capability i.e., -20 V during GCT turn-off and blocking)
Implementation Method 3
The tilted arrows in FIG. 1 show the expected plasma spread in GCT mode operation, which can be inverted for the diode mode
Implementation Method 4
In high voltage devices like BGCTs 1' usually the N--base (N-drift layer) is very low doped and if the separation region distance is small, there is a possibility for the punch through effect
Data Source
AI summary
A reverse-conducting power semiconductor device (1) with a wafer (10) having a first main side (11) and a second main side (15), which is arranged parallel to the first main side (11), is provided. The device comprises a plurality of diode cells (96) and a plurality of GCT cells (91), wherein each GCT cell comprises layers in the following order between the first and second main side (11, 15): - a thyristor cathode electrode (2), - a thyristor cathode layer (4) of the first conductivity type, - a thyristor base layer (6) of the second conductivity type, - a drift layer (3) of the first conductivity type, - a thyristor buffer layer (8) of the first conductivity type, - a thyristor anode layer (5) of the second conductivity type, and - a thyristor anode electrode (25). Each GCT cell (91) further comprises a gate electrode (7), which is arranged lateral to the thyristor cathode layer (4) and separated from it by the thyristor base layer (6). Each diode cell (96) comprises a diode anode electrode (28) on the first main side (11), which is in contact to a diode anode layer (55) of the second conductivity type, which diode anode layer (55) is separated from the thyristor base layer (6) by the drift layer (3), a diode drift layer 3", a diode cathode layer (45) of the first conductivity type on the second main side (15), which is arranged alternating to the thyristor anode layer (5), and a diode cathode electrode. The device comprises at least one mixed part (99), in which the diode anode layers (55) of the diode cells (96) alternate with the first cathode layers (4) of the GCT cells (91). In each diode cell (96) a diode buffer layer (32) of the first conductivity type is arranged between the diode anode layer (55) and the drift layer (3) such that the diode buffer layer (32) covers lateral sides of the diode anode layer (55) from the first main side (11) at least to a depth of 90 % of the thickness of the diode anode layer (55).