Cascaded RC Glitch Filter With Feedback for Low-Skew Pulses
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Low frequency interfaces in Integrated Circuits (ICs) prone to picking up external noise due to low slew rates, leading to timing and functional failures, and conventional glitch filters suffer from duty cycle distortion, pulse dipping, and supply noise susceptibility.
Innovation Solution
A glitch filter with at least two coupled RC filters and feedback/feedforward switches to minimize delay skews and stabilize output voltages, preventing noise in output signals by efficiently pulling up or down the output voltage based on input signals and reverting to previous rail conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional analog RC circuit is used for glitch filtering, then glitches of specified pulse widths can be suppressed, but duty cycle distortion and pulse dipping occur
Solution Approach 1:
The glitch filter is divided into multiple independent RC filter stages (first RC filter, second RC filter) connected in series. Each stage processes the signal independently, allowing the filter to suppress glitches while maintaining duty cycle accuracy through the cumulative effect of multiple stages rather than relying on a single complex RC circuit.
Solution Approach 2:
Feedback switches are implemented to detect and correct duty cycle distortion and pulse dipping in real-time. The feedback mechanism monitors the output signal characteristics and adjusts the filtering action to compensate for distortions, ensuring that glitch suppression does not compromise duty cycle accuracy.
2Reliability
If a conventional analog RC circuit is used for glitch filtering, then glitches can be suppressed, but supply noise susceptibility increases
Solution Approach 1:
By segmenting the filter into multiple RC stages, each stage contributes to noise rejection. The cascaded structure provides cumulative filtering effect that suppresses supply noise more effectively than a single RC circuit, as each stage attenuates high-frequency noise components.
Solution Approach 2:
The multiple RC filter stages act as intermediary elements between the noisy supply and the output signal. Each RC stage serves as a noise barrier, progressively filtering out supply noise while allowing the desired signal to pass through with minimal distortion.
3Reliability
If glitch filtering is implemented, then timing failures can be prevented, but delay skews are introduced
Solution Approach 1:
The delay introduced by each RC stage is distributed across multiple stages rather than concentrated in a single stage. This segmentation allows for better control and balancing of delays, reducing overall delay skew while maintaining effective glitch filtering capability.
Solution Approach 2:
The resistor and capacitor values in each RC stage are carefully selected and optimized to achieve the desired filtering effect while minimizing delay skew. By adjusting these parameters across multiple stages, the filter achieves optimal balance between glitch suppression and delay characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses glitches, reduces delay skews, and enhances noise immunity, resulting in sharper rising and falling edges and improved pulse width retention, immune to supply noise.
Implementation Method 1
A glitch filter with at least two coupled RC filters to minimize delay skews based on a RC filter or an inverter of the glitch filter
Implementation Method 2
A glitch filter with feedback and feedforward switches coupled to a RC filter to efficiently pull up or pull down an output voltage of the RC filter to rails and prevent noises in output signals
Data Source
AI summary
An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switches to the feedback switches to accelerate the pull up or the pull down.