RC-IGBT Cathode Layout to Limit Current Bypass

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Solution Overview

Problem

Current semiconductor devices with integrated RC-IGBTs face challenges in optimizing the arrangement of the cathode region to enhance forward current density and peak surge current characteristics, as existing configurations can lead to current bypass pathways and reduced electrical performance.

Innovation Solution

The semiconductor device incorporates a cathode region arranged at specific reference positions relative to the gate and well connection electrodes, forming linear current pathways to increase forward current and peak surge current, while avoiding configurations that promote current bypass, by defining permitted and prohibited ranges for the cathode region's placement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the cathode region is arranged at arbitrary positions, then device fabrication is simplified, but current bypass pathways occur and electrical performance deteriorates

Engineering Contradiction:
Improveelectrical performanceVSAvoidcathode region arrangement constraints
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by defining specific permitted and prohibited ranges for cathode region arrangement. Instead of uniform constraints across the entire device, the solution creates localized zones (permitted ranges centered at reference positions and prohibited ranges adjacent to gate/well connection electrodes) that optimize current flow paths. This allows the cathode region to be positioned in areas that enhance forward current density while avoiding regions that would create harmful current bypass pathways.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250022874A1Semiconductor device
Publication Date: 2025.01.16 ROHM CO LTD
  • US20250022874A1 patent drawing
  • US20250022874A1 patent drawing
  • US20250022874A1 patent drawing

AI summary

A semiconductor device includes a chip that has a first main surface on one side and a second main surface on the other side, an IGBT region provided in an inner portion of the first main surface, an outer peripheral region provided in a peripheral edge portion of the first main surface, a first conductivity type well region formed in a surface layer portion of the first main surface in the outer peripheral region so as to define the IGBT region, an insulating film that covers the well region, a well connection electrode embedded in the insulating film so as to be connected to the well region, and a second conductivity type cathode region formed in a surface layer portion of the second main surface in the outer peripheral region so as to oppose the well connection electrode, and that forms a diode with the well region.