RC-IGBT Layout Optimizes Channel-Cathode Distance

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Solution Overview

Problem

Conventional techniques for reverse conducting insulated gate bipolar transistors (RC-IGBTs) result in a relatively large distance between the current sense region and the cathode layer due to neglecting the thickness of the semiconductor substrate, leading to potential interference between these components.

Innovation Solution

The semiconductor device design minimizes the distance between the channel in the current sense region and the cathode layer by optimizing the layout and doping concentrations, ensuring the channel and cathode layer do not interfere with each other, while maintaining a predetermined relational expression for distances and semiconductor properties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the distance between the current sense region and the cathode layer is reduced to minimize device size, then the device becomes more compact, but the channel and cathode layer may interfere with each other

Engineering Contradiction:
Improvedevice sizeVSAvoidinterference between channel and cathode layer
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent utilizes the thickness direction (vertical dimension) of the semiconductor substrate to reduce the in-plane distance between the current sense region and cathode layer. By considering and optimizing the three-dimensional spatial arrangement, including the thickness direction, the design achieves closer proximity without interference, effectively reducing device footprint while maintaining reliability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If a predetermined relational expression is established between distance W, distance S, diffusion coefficient D, and lifetime τ, then interference between channel and cathode layer is prevented, but device design complexity increases

Engineering Contradiction:
Improveprevention of interferenceVSAvoiddesign complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent establishes a predetermined relational expression involving parameters W (distance in in-plane direction), S (distance in thickness direction), D (diffusion coefficient), and τ (lifetime). By defining quantitative relationships between these parameters, the patent provides clear design criteria that guide the optimization process, making the complex interference prevention requirement manageable through parameter control.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively reduces the electron current flowing into the cathode layer, allowing for a more compact and efficient RC-IGBT structure without interference, thereby enhancing performance and reducing size.

Implementation Method 1

a diffusion coefficient and a lifetime of a part of the semiconductor substrate between the channel of the first semiconductor layer and the third semiconductor layer are designated as D and τ, respectively

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 2

a lifetime of a part of the semiconductor substrate between the channel of the first semiconductor layer and the third semiconductor layer are designated as D and τ, respectively

Methodology Applied
Scientific EffectCarrier recombination:

Data Source

PatentUS11495663B2Semiconductor device including insulated gate bipolar transistor, diode, and current sense regions
Publication Date: 2022.11.08 MITSUBISHI ELECTRIC CORP
  • US11495663B2 patent drawing
  • US11495663B2 patent drawing
  • US11495663B2 patent drawing

AI summary

A predetermined relational expression holds where a first distance along the in-plane direction from a channel of the first semiconductor layer to a third semiconductor layer that is the other of the collector layer and the cathode layer is designated as W, a second distance from the channel of the first semiconductor layer to the second semiconductor layer is designated as S, and a diffusion coefficient and a lifetime of a part of the semiconductor substrate between the channel of the first semiconductor layer and the third semiconductor layer are designated as D and τ, respectively.