RC-IGBT Diode Region Gate Interference Suppression
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Solution Overview
Problem
The RC-IGBT semiconductor devices experience 'gate interference,' which affects the stability of the diode operation due to the Schottky connection in the diode structure, leading to unstable current flow.
Innovation Solution
The semiconductor device design incorporates a diode region with n-type pillar regions connected by Schottky contacts, where the on-resistance of the first pillar region is higher than the second pillar region, closer to the IGBT region, making it harder for the p-n junction to turn on near the second pillar region, thereby minimizing the effect of gate interference on the diode's current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a Schottky connection is used in the diode structure, then the diode can be integrated with the IGBT in a single semiconductor substrate, but gate interference occurs that affects the stability of diode operation
Solution Approach 1:
The patent applies local quality by creating spatial variation in the n-type impurity concentration across different regions of the diode. Specifically, the n-type impurity concentration in the drift region is set to be lower than in the barrier region, and the pillar regions have different concentrations based on their distance from the IGBT region. This local differentiation allows the diode structure to simultaneously achieve integration with the IGBT while suppressing gate interference effects in critical areas.
Solution Approach 2:
The patent employs parameter changes by systematically varying the n-type impurity concentration across different regions of the diode structure. The barrier region has a higher n-type impurity concentration than the drift region, and pillar regions closer to the IGBT have different concentrations than those farther away. These parameter variations enable the device to maintain both integration capability and operational stability by optimizing the electrical characteristics of each region.
2Reliability
If the on-resistance of pillar regions is reduced to improve current flow, then the diode conducts better, but gate interference effects are amplified
Solution Approach 1:
The patent applies local quality by assigning different on-resistance values to pillar regions based on their spatial location. Pillar regions farther from the IGBT have lower on-resistance to ensure good current conduction, while pillar regions closer to the IGBT have higher on-resistance to suppress gate interference. This spatial differentiation of electrical properties allows the diode to achieve both low overall resistance and high immunity to gate interference.
Solution Approach 2:
The patent converts the potentially harmful effect of gate interference into a beneficial design feature by strategically placing higher resistance pillar regions near the IGBT. These higher resistance regions act as natural barriers that prevent gate interference from propagating into the diode's current path, thereby transforming what could be a detrimental effect into a protective mechanism.
3Speed
If the p-n junction is made easier to turn on to improve diode switching speed, then the diode responds faster, but the Schottky connection becomes unstable
Solution Approach 1:
The patent employs parameter changes by optimizing the n-type impurity concentration distribution to achieve the desired balance between switching speed and Schottky connection stability. The drift region has a lower n-type impurity concentration that facilitates faster switching, while the barrier region and certain pillar regions have higher concentrations that maintain Schottky connection stability and prevent unwanted turn-on behavior.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the impact of gate interference on the overall diode operation, ensuring stable current flow and minimizing snapback occurrences, as the p-n junctions near the second pillar region are harder to turn on, resulting in a semiconductor device less susceptible to gate interference.
Implementation Method 1
The n-type pillar region is connected to an anode electrode by a Schottky contact
Implementation Method 2
a p-type anode region connected to the anode electrode by an Ohmic contact
Data Source
AI summary
A technology for inhibiting gate interference in an RC-IGBT employing a diode structure having Schottky connections is provided. A semiconductor device includes a semiconductor substrate including a diode region and an IGBT region. In this semiconductor device, the diode region includes: a p-type anode region connected to an anode electrode by an Ohmic contact; a plurality of n-type pillar regions connected to the anode electrode by Schottky contacts; an n-type barrier region; an n-type diode drift region; and an n-type cathode region. An on-resistance of a first pillar region with respect to the anode electrode is higher than an on-resistance of a second pillar region with respect to the anode electrode. The second pillar region is located at a position close to the IGBT region.