RC-IGBT Diode Layout for Higher FWD Breakdown Withstand
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Solution Overview
Problem
In Reverse Conducting IGBTs (RC-IGBTs), the destructive breakdown withstand capability in the Free Wheeling Diode (FWD) region is reduced, posing a technical challenge in maintaining the device's performance.
Innovation Solution
The semiconductor device incorporates a gate runner portion and a first conductivity type well region, with a diode region featuring a plurality of first contact portions, a first conductivity type anode region, and a second conductivity type cathode region. The well region contacts the diode region, and specific distances and arrangements are defined to enhance the breakdown withstand capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the well region is positioned closer to the first contact portions to reduce manufacturing complexity, then the manufacturing precision is improved, but the hole current concentration in the FWD region increases, reducing the destructive breakdown withstand capability
Solution Approach 1:
The patent resolves the contradiction by transitioning from a two-dimensional planar layout to a three-dimensional vertical structure. The well region is positioned at a specific depth below the gate runner portion, creating a vertical separation that reduces hole current concentration in the FWD region while maintaining manageable manufacturing complexity through controlled doping depth.
Solution Approach 2:
The patent applies local quality by creating a non-uniform dopant concentration distribution in the well region. The well region has a first conductivity type dopant concentration that varies with depth, with higher concentration near the gate runner portion and lower concentration deeper in the substrate. This localized variation optimizes both the electrical performance (reducing hole concentration) and manufacturing feasibility.
2Reliability
If the well region is positioned deeper in the substrate to reduce hole concentration, then the destructive breakdown withstand capability is improved, but the manufacturing complexity and difficulty increase
Solution Approach 1:
The patent manages complexity by utilizing the vertical dimension (depth) rather than increasing lateral complexity. The well region is positioned at a specific depth range (from the upper surface to a depth between 5-20 μm) with controlled dopant concentration, creating a simple vertical structure that achieves hole current reduction without complicating the overall device architecture.
Solution Approach 2:
The patent resolves the complexity issue by changing the dopant concentration parameter in the well region. By controlling the first conductivity type dopant concentration to be higher than the anode region but with a specific depth profile, the patent achieves effective hole current management while maintaining a manufacturable structure with well-defined parameters.
3Ease of manufacture
If the distance between the well region and first contact portions is reduced to simplify manufacturing, then the ease of manufacture is improved, but the hole current concentration increases, reducing breakdown withstand capability
Solution Approach 1:
The patent resolves this contradiction by moving the well region to a different vertical level rather than reducing lateral distance. The well region is positioned below the gate runner portion at a specific depth, creating vertical separation that reduces hole current concentration while maintaining ease of manufacture through standard doping processes that can precisely control depth.
Solution Approach 2:
The gate runner portion acts as an intermediary structure between the well region and the first contact portions. The well region is positioned below the gate runner portion, which mediates the spatial relationship and allows for optimized positioning that balances manufacturing ease with electrical performance by controlling the vertical distance and dopant distribution.
4Ease of manufacture
If the well region dopant concentration is increased to improve manufacturing tolerance, then the ease of manufacture is improved, but the hole current concentration in the FWD region increases, reducing breakdown withstand capability
Solution Approach 1:
The patent applies local quality by creating a depth-dependent dopant concentration profile in the well region. The first conductivity type dopant concentration is higher near the gate runner portion (providing manufacturing tolerance) and decreases with depth (reducing hole current concentration). This localized variation allows the patent to simultaneously achieve manufacturing ease and electrical performance.
Solution Approach 2:
The patent resolves the contradiction by changing the dopant concentration parameter as a function of depth. By controlling the dopant concentration to decrease with depth from the gate runner portion, the patent achieves a balance where the upper region provides manufacturing tolerance while the lower region reduces hole current concentration, optimizing both manufacturing ease and breakdown withstand capability.
Data Source
AI summary
Provided is a semiconductor device that includes a first conductivity type well region below a gate runner portion, wherein a diode region includes first contact portions, a first conductivity type anode region, and a second conductivity type cathode region; wherein the well region contacts the diode region in the first direction, and when an end of the well region, an end of at least one of first contact portions, and an end of the cathode region that face one another in the first direction are imaginary projected on an upper surface of the semiconductor substrate, a first distance is longer than a second distance, the first distance being a distance between the end of the well region and the end of the cathode region, and the second distance being a distance between the end of the well region and the end of the at least one first contact portion.