RC-IGBT Gate Pulse Overlap for Switching Loss Reduction
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Solution Overview
Problem
Current methods for controlling reverse-conducting insulated bi-polar transistors (RC-IGBTs) do not adequately minimize switching losses, particularly due to the timing of desaturation pulses in half-bridge configurations, which can lead to increased thermal cycling and reduced semiconductor lifetime.
Innovation Solution
The method involves overlapping gate pulses for complementary switch components in a half-bridge configuration, with a pre-trigger pulse applied to the RC-IGBT in reverse conduction mode, ensuring that both switches receive turn-on signals simultaneously for a controlled period, thereby minimizing the reverse recovery current peak and switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a desaturation pulse is applied to the RC-IGBT before the complementary switch receives its gate pulse, then switching losses are reduced, but switching losses are not minimized and thermal cycling issues persist
Solution Approach 1:
A pre-trigger pulse is applied to the RC-IGBT gate before the complementary switch turns on, preparing the RC-IGBT for reverse conduction mode. This preliminary action reduces excess carriers in the drift region before the switching event, thereby minimizing reverse recovery current peak and switching losses while reducing thermal cycling stress
Solution Approach 2:
The gate pulse timing is dynamically adjusted to create an overlap period where both the RC-IGBT and complementary switch receive turn-on signals simultaneously. This dynamic timing control optimizes the transition process, ensuring minimal switching losses while maintaining safe operating conditions through controlled carrier distribution
2Ease of operation
If standard switching pulses are applied to the RC-IGBT gate, then the RC-IGBT operates as an IGBT, but switching losses increase and thermal cycling issues arise
Solution Approach 1:
During the overlap period, periodic gate pulsing is applied to both the RC-IGBT and complementary switch. This periodic action maintains both devices in a controlled conducting state, allowing the RC-IGBT to operate in reverse conduction mode with minimized switching losses while preventing excessive thermal cycling
Solution Approach 2:
The gate voltage parameters are changed during the overlap period to optimize switching performance. By adjusting the gate pulse timing and duration, the excess carrier distribution is controlled, minimizing reverse recovery current and switching losses while maintaining safe operation
3Extent of automation
If the desaturation pulse is applied and ended before the complementary switch gate pulse, then the RC-IGBT can be controlled, but losses are not minimized
Solution Approach 1:
The desaturation pulse and complementary switch gate pulse are merged in time to create an overlap period. During this overlap, both pulses are active simultaneously, allowing the RC-IGBT to transition to reverse conduction mode with minimized switching losses. This merging of pulse timing optimizes both control capability and loss reduction
Data Source
Figure 1~2
Figure 3~4
Figure 5~7(b)
AI summary
A method and an arrangement of controlling a reverse-conducting IGBT (RC-IGBT) component in a circuit comprising a series connection of controllable switch components where at least one of the controllable switch components is an RC-IGBT and the other component is to be controlled to a conductive state. The method comprising applying a pre-trigger pulse to the gate electrode of the RC-IGBT during reverse conduction of the RC-IGBT at a first time instant (t1), the pre-trigger pulse corresponding to a turn-on gate pulse, applying a turn-on gate pulse at a second time instant (t2) to the other controllable switch component of the series connection for controlling the other controllable switch component to a conductive state such that the pre-trigger pulse and the turn-on gate pulse overlap, and ending the pre-trigger pulse after a delay time at the third time instant (t3), the delay time being the time period when the turn-on gate pulse and the pre-trigger pulse overlap.