RC-IGBT p-type Base Layer Design for Recovery Current Control
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Solution Overview
Problem
The existing reverse conducting insulated gate bipolar transistors (RC-IGBTs) face issues with increased recovery current and potential drop in withstand voltage due to the high impurity concentration and depth of the p+-type well layer in the wiring region, which can lead to destruction during abrupt switching operations.
Innovation Solution
A semiconductor device design where the p-type base layer in the wiring region has a lower impurity concentration and smaller depth compared to the p+-type well layer in the termination region, with the p-type base layer being common to both regions, and an insulating film is used to connect the gate electrode to the IGBT, reducing the recovery current and maintaining high withstand voltage without additional manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p+-type well layer with high impurity concentration and large depth is formed in the wiring region, then the diode performance is improved, but the recovery current increases
Solution Approach 1:
The patent applies local quality by forming a p-type base layer with lower impurity concentration and smaller depth specifically in the wiring region, while maintaining the p+-type well layer with high impurity concentration and large depth in the termination region. This localized differentiation allows the diode in the wiring region to have reduced recovery current while the termination region maintains its voltage-withstanding capability.
2Object-generated harmful factors
If the impurity concentration and depth of the p layer are reduced in the wiring region, then the recovery current is reduced, but the withstand voltage may drop
Solution Approach 1:
The patent resolves this contradiction by applying different layer characteristics to different regions: the wiring region uses a p-type base layer with lower impurity concentration and smaller depth to reduce recovery current, while the termination region maintains a p+-type well layer with high impurity concentration and large depth to ensure withstanding voltage. This spatial differentiation of material properties allows both requirements to be satisfied simultaneously.
3Device complexity
If the p+-type well layer with high impurity concentration and large depth is formed in the wiring region, then the diode structure is simplified, but the breakdown voltage decreases
Solution Approach 1:
The patent maintains structural simplicity in the wiring region by forming a p-type base layer that is still a single continuous layer, avoiding the need for complex multi-step formation processes. Meanwhile, the termination region retains the p+-type well layer configuration for high breakdown voltage. The local differentiation of layer parameters achieves both structural simplicity and high reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively inhibits the increase in recovery current and achieves high withstand voltage and breakdown voltage while maintaining cost-effectiveness and performance by reducing the supply of holes and concentrating electric fields in the termination region.
Implementation Method 1
the p-type base layer is provided in common to the wiring region and the cell region and has a lower impurity concentration and a smaller depth than the p-type well layer
Implementation Method 2
an insulating film is used to connect the gate electrode to the IGBT
Implementation Method 3
concentrating electric fields in the termination region
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate having a cell region, a termination region located around the cell region, and a wiring region; an IGBT provided in the cell region; an insulating film provided on the semiconductor substrate in the wiring region; a gate electrode provided on the insulating film and connected to a gate of the IGBT; a p-type well layer provided on a surface side of the semiconductor substrate in the termination region; and a diode provided in the wiring region, wherein the diode includes a the p-type base layer provided on the surface side of the semiconductor substrate and an n-type cathode layer provided on a reverse side of the semiconductor substrate, the p-type base layer is provided in common to the wiring region and the cell region and has a lower impurity concentration and a smaller depth than the p-type well layer.