RC-IGBT Second Gate Control for Carrier Discharge
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Solution Overview
Problem
The existing reverse-conducting insulated gate bipolar transistors (RC-IGBTs) face challenges in reducing chip size while maintaining operational stability, as the large boundary region required to manage carriers in the drift region increases the chip size and can lead to unstable operation due to delayed discharge of remaining carriers.
Innovation Solution
The RC-IGBT design includes a semiconductor layer with a second gate electrode connected to a second gate electrode pad, allowing independent control of the second gate voltage, which promotes the discharge of holes from the drift region by making it negative before changing the first gate voltage from turn-on to turn-off, reducing the need for a large boundary region and thus minimizing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large boundary region is provided between the IGBT and diode regions, then carrier management is improved, but chip size increases
Solution Approach 1:
The boundary region is divided into multiple sub-regions with different impurity concentrations (first boundary sub-region with higher concentration, second boundary sub-region with lower concentration). This segmentation allows efficient carrier management in each sub-region, reducing the total boundary region area needed while maintaining reliability.
Solution Approach 2:
Different impurity concentrations are applied to different parts of the boundary region. The first boundary sub-region has a higher impurity concentration than the second boundary sub-region, creating local quality variations that optimize carrier discharge performance across the boundary region without requiring a uniformly large area.
2Area of stationary object
If the boundary region area is reduced, then chip size decreases, but carrier discharge becomes delayed causing unstable operation
Solution Approach 1:
The boundary region is segmented into sub-regions with gradient impurity concentrations, where the first boundary sub-region (closer to IGBT region) has higher concentration and the second boundary sub-region (closer to diode region) has lower concentration. This segmentation enables efficient carrier discharge within a smaller total area, maintaining operation stability while reducing chip size.
Solution Approach 2:
The impurity concentration parameter is varied across the boundary region, with the first boundary sub-region having a higher impurity concentration than the second boundary sub-region. This parameter change optimizes the carrier discharge characteristics, allowing stable operation with a reduced boundary region area and smaller chip size.
Data Source
AI summary
A semiconductor device of the embodiment includes a semiconductor layer including a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a fifth semiconductor region, a sixth semiconductor region, a first trench, and a second trench, a first gate electrode in the first trench; a second gate electrode in the second trench; a first electrode on a first face side; a second electrode on a second face side; a first electrode pad connected to the first gate electrode; and a second electrode pad connected to the second gate electrode. The semiconductor device includes a first region including the first semiconductor region; a second region including the second semiconductor region; and a third region provided between the first region and the second region, the third region having a density of the second trench higher than that of the first region.