RC-IGBT Control Circuit with Segmented Gate Pulse Timing

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Solution Overview

Problem

Existing semiconductor devices, such as IGBTs, face challenges in minimizing loss during operation due to high gate capacitance and reduced switching speed when attempting to reduce loss through increased channel numbers.

Innovation Solution

A control circuit and semiconductor device configuration that applies independent pulses to multiple gates, optimizing pulse timing to maintain low gate capacitance and high switching speed while reducing loss, by differing the start and end times of pulses applied to the first and second gates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the number of channels is increased to reduce loss, then loss is reduced, but gate capacitance increases and switching speed decreases

Engineering Contradiction:
ImprovelossVSAvoidswitching speed
Core Design Contradiction:
Loss of energyVSSpeed

Solution Approach 1:

The patent divides the gate control into multiple independent gates (first gate and second gate) with separate control terminals. This segmentation allows independent pulse application to each gate, enabling optimized switching control that reduces loss without requiring increased channel numbers, thereby maintaining high switching speed while achieving loss reduction

Inventive Principle:
Principle #1Segmentation

2Loss of energy

If the number of channels is increased to reduce loss, then loss is reduced, but gate capacitance increases

Engineering Contradiction:
ImprovelossVSAvoidgate capacitance
Core Design Contradiction:
Loss of energyVSQuantity of substance

Solution Approach 1:

The gate is segmented into multiple independent gates (first gate and second gate), each controlled separately. This allows the use of multiple channels with optimized pulse timing rather than increasing the number of parallel channels, thereby reducing loss while keeping the total gate capacitance manageable through controlled switching sequences

Inventive Principle:
Principle #1Segmentation

3Speed

If pulses are applied simultaneously to multiple gates, then switching speed is high, but loss increases

Engineering Contradiction:
Improveswitching speedVSAvoidloss
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent applies preliminary action by controlling the timing of pulses to the first and second gates differently. The pulse timing is optimized so that one gate is activated before the other, allowing the switching process to begin in advance through coordinated sequential activation, achieving both high switching speed and reduced loss through optimized pulse sequences

Inventive Principle:
Principle #10Preliminary action

4Loss of energy

If pulse timing is optimized with different start and end times for multiple gates, then loss is suppressed and switching speed is maintained, but control complexity increases

Engineering Contradiction:
ImprovelossVSAvoidcontrol complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent implements dynamic control by allowing different pulse timing configurations for the first and second gates. The control circuit dynamically adjusts pulse start and end times based on operational requirements, enabling optimized loss suppression and switching speed maintenance through adaptive, flexible pulse timing rather than fixed simultaneous control

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10778216B2Control circuit, semiconductor device, and electrical circuit device
Publication Date: 2020.09.15 KK TOSHIBA
  • US10778216B2 patent drawing
  • US10778216B2 patent drawing
  • US10778216B2 patent drawing

AI summary

According to one embodiment, a control circuit is connected to an element portion including a first element. The first element is an RC-IGBT. The first element includes a first gate, a first other gate, a first collector, and a first emitter. The control circuit performs a first operation and a second operation. In at least a portion of the first operation, the control circuit causes a first current to flow from the first collector toward the first emitter. In at least a portion of the second operation, the control circuit causes a second current to flow from the first emitter toward the first collector. In the second operation, the control circuit supplies a first pulse to the first gate and supplies a first other pulse to the first other gate. The first pulse has a first start time and a first end time.