RC Characteristic-Based Layer Assignment for Clock Network Timing
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Solution Overview
Problem
Conventional routing and layer assignment processes in electronic design automation (EDA) do not consider resistance or capacitance characteristics, leading to timing issues in circuit designs due to huge resistance or capacitance differences in clock networks.
Innovation Solution
The method involves assigning layers for circuit designs based on resistance or capacitance characteristics, grouping layers with similar RC values, and enlarging the layer range for non-routed networks to minimize RC differences, thereby improving timing and layer adherence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional layer assignment processes are used without considering resistance or capacitance characteristics, then the routing process is simpler and faster, but timing issues arise due to huge resistance or capacitance differences in clock networks
Solution Approach 1:
The patent applies parameter changes by transitioning from conventional layer assignment that ignores electrical characteristics to a new approach that incorporates resistance and capacitance values as key parameters. The system calculates RC characteristics for different layers and uses these parameters to guide layer assignment, thereby resolving the timing issues caused by huge RC differences while maintaining a systematic and manageable process complexity.
Solution Approach 2:
The patent implements preliminary action by pre-calculating and storing resistance and capacitance characteristics for each layer before the actual routing process. This preliminary characterization of layers enables the routing algorithm to make informed decisions about layer assignment, avoiding timing issues before they occur rather than correcting them afterward.
2Reliability
If layers with huge resistance or capacitance differences are used for clock network routing, then more layer options are available, but slew delay and insertion delay increase
Solution Approach 1:
The patent applies local quality by matching the electrical characteristics of each layer to the specific requirements of different clock networks. Instead of using a uniform layer selection criterion, the system evaluates RC characteristics locally for each layer and assigns layers based on the specific needs of each clock network, thereby minimizing slew delay and insertion delay while maintaining appropriate layer selection flexibility.
3Manufacturing precision
If layer assignment does not consider RC characteristics, then the routing process is faster, but timing closure becomes difficult to achieve
Solution Approach 1:
The patent implements preliminary action by pre-calculating and storing resistance and capacitance characteristics for each layer before the actual routing process. This preliminary characterization of layers enables the routing algorithm to make informed decisions about layer assignment, avoiding timing issues before they occur rather than correcting them afterward.
Solution Approach 2:
The patent replaces the conventional mechanical/geometric layer assignment approach with an electrical characteristic-based system. Instead of relying solely on physical layer properties and routing geometry, the system substitutes electrical parameters (resistance and capacitance) as the primary basis for layer selection, thereby achieving both timing accuracy and routing efficiency.
Data Source
AI summary
Various embodiments provide for layer assignment of a network of a circuit design based on a resistance or capacitance characteristic, such as a resistance/capacitance characteristic associated with a layer, a wire, or a via of the circuit design. In particular, various embodiments consider a resistance/capacitance characteristic of a layer, a wire, or a via of a circuit design to determine a set of layers for routing one or more networks of the circuit design, which can enable some embodiments to route the networks on the layers within a certain range that has very close resistance/capacitance (RC) characteristics, and can permit routing each network on layers having the smallest RC characteristic difference.