RC Oscillator Comparator Offset Compensation Without Flip-Flop
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Solution Overview
Problem
Conventional RC oscillators are susceptible to comparator offset voltages, which alter the frequency of the generated clock signal, leading to unintended frequency deviations.
Innovation Solution
The RC oscillator design incorporates charging/discharging circuitry that adjusts initial voltage levels based on the comparator reference voltage, making the oscillator less sensitive to comparator offset voltages by maintaining symmetrical voltage levels around the comparator reference voltage, thereby stabilizing the clock signal frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional RC oscillator uses a comparator with offset voltage, then the oscillator can generate clock signals, but the frequency of the clock signal becomes unintended and inaccurate
Solution Approach 1:
The patent applies asymmetry by using different reference voltages for the charging and discharging phases. Specifically, during charging, the reference voltage is set to one level, and during discharging, it is set to a different level. This asymmetric reference voltage scheme compensates for the comparator offset voltage, allowing the clock signal frequency to remain accurate despite the presence of offset voltage in the comparator.
2Ease of operation
If a D-type flip-flop is used to correct duty cycle, then the clock signal can achieve 50% duty cycle, but the device complexity and power consumption increase
Solution Approach 1:
The patent extracts and removes the D-type flip-flop from the oscillator circuit. Instead of using a flip-flop to correct the duty cycle, the invention directly generates a 50% duty cycle clock signal through the asymmetric reference voltage charging/discharging mechanism. This elimination of the flip-flop reduces device complexity and power consumption while maintaining accurate duty cycle.
3Speed
If a D-type flip-flop is used to divide frequency, then the clock signal can achieve desired frequency, but the power consumption increases
Solution Approach 1:
The patent removes the D-type flip-flop from the circuit, eliminating its power consumption. The desired clock signal frequency is achieved directly through the RC charging/discharging time constants combined with the asymmetric reference voltage scheme, without requiring the flip-flop for frequency division. This significantly reduces the overall power consumption of the oscillator.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design results in a clock signal frequency that is relatively insensitive to comparator offset voltages, reducing frequency deviations and eliminating the need for a D-type flip-flop, leading to potential power savings and improved reliability.
Implementation Method 1
a capacitor C, a comparator 102
Implementation Method 2
a resistor R
Implementation Method 3
a comparator 102, three inverters 104, 106, and 110
Data Source
AI summary
A comparator-based oscillator generates an output frequency that is relatively independent of comparator offset voltages. Charging/discharging circuitry controls the comparator input voltage, and logic circuitry generates the oscillator output (e.g., clock) signal and controls the charging/discharging circuitry. During an oscillator charging cycle, the charging/discharging circuitry drives the voltage at the comparator input node from a relatively low initial charging voltage level up to the comparator reference voltage. During an oscillator discharging cycle, the charging/discharging circuitry drives the voltage at the comparator input node from a relatively high initial discharging voltage level down to the comparator reference voltage. The initial charging and discharging voltage levels depend on the comparator reference voltage, such that a comparator offset voltage directly affects the initial charging and discharging voltage levels, thereby keeping the output frequency relatively unchanged.