On-Chip RC Oscillator Chopping Circuit for RTN-Stable Timing
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Solution Overview
Problem
Low-drift fully integrated low power oscillators in system-on-chip (SOC) are susceptible to Random Telegraph Noise (RTN) noise, which affects the precision of timing in sleep modes, particularly in battery-powered RF-SOC applications, where minimized power consumption and low supply voltages are crucial.
Innovation Solution
The implementation of chopping switches between MOS transistors and the control resistor, alternating current sources M1 and M2 for 50% of the time, reduces the sensitivity to RTN noise by commuting the current in each connection branch, thereby stabilizing the oscillator's frequency output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a fully integrated LD-RC oscillator is used in deep submicron CMOS technologies, then power consumption is minimized and integration is achieved, but sensitivity to Random Telegraph Noise (RTN) increases, reducing timing precision
Solution Approach 1:
The patent combines two current sources M1 and M2 in a differential configuration, where both current sources are active simultaneously but contribute equally to the oscillator frequency. This merging approach averages out RTN effects from individual transistors, reducing sensitivity while maintaining low power consumption and timing precision in deep submicron CMOS technologies.
2Device complexity
If conventional current sources are used in the oscillator, then circuit simplicity is maintained, but RTN noise susceptibility increases, affecting frequency stability
Solution Approach 1:
The patent merges two current sources M1 and M2 in a differential configuration, where both current sources are active simultaneously but contribute equally to the oscillator frequency. This merging approach averages out RTN effects from individual transistors, reducing sensitivity while maintaining low power consumption and timing precision in deep submicron CMOS technologies.
Data Source
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AI summary
A system with a low-drift on-chip (LD-RC) oscillator (10) with lowered sensitivity to Random Telegraph Noise when generating a current (Id) for the LD-RC oscillator (10). A control resistor (R) is connected through an intermediary arrangement (50) to one of a first MOS transistor (M1) or of a second MOS transistor (M2) between two terminals of a supply voltage source (Vdd, GND). The gate of the first MOS transistor (M1) is connected to the gate of the second MOS transistor (M2), whereas the source of the first MOS transistor (M1) and the source of the second MOS transistor (M2) are connected to one terminal of the supply voltage source (Vdd), the control resistor (R) being connected to the other opposite terminal of the supply voltage source (GND). The intermediary arrangement (50) includes first, second, third and fourth controlled chopping switches (S1A, S1B, S2A, S2B) placed between the control resistor (R) and the first and second MOS transistors (M1, M2), and between the RC oscillator (10) and the first and second MOS transistors (M1, M2). The first and second switches are conductive in a first phase (PH1) to connect the resistor to the first MOS transistor, and the oscillator to the second MOS transistor. The third and fourth switches are conductive in a second phase (PH2) to connect the resistor to the second MOS transistor, and the oscillator to the first MOS transistor. The control signals (PH1) and (PH2) serve as "chopping" signals. Filtering of the "chopping" frequency is accomplished in the digital counter serving as digital integrator / low pass filter.