RC Oscillator Watchdog Circuit for Stuck-State Reset
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Standard RC oscillators can become stuck due to component variation errors, leading to failure in generating a clock signal, which hampers the startup operations of System on a Chip (SoC) devices.
Innovation Solution
A watchdog circuit is introduced that includes a capacitive node, charge circuitry, discharge circuitry, and triggering circuitry to detect faults in the RC oscillator. The circuit selectively charges and discharges the capacitive node based on the logic output signal, asserting a reset signal when a fault is detected, thereby resetting the RC oscillator to restore proper operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If an RC oscillator is used to provide a clock signal during startup, then the startup time is reduced, but the oscillator may become stuck due to component variation errors
Solution Approach 1:
The patent applies preliminary action by implementing a watchdog circuit that proactively monitors the RC oscillator before it can become stuck. The circuit continuously checks the oscillator's output signal and prepares a reset mechanism in advance, so that if the oscillator fails to transition properly, the reset can be triggered immediately without waiting for the failure to manifest in the SoC operation.
Solution Approach 2:
The patent implements feedback by creating a closed-loop monitoring system where the watchdog circuit observes the RC oscillator's output and feeds this information back to a reset mechanism. The feedback loop includes a capacitive node that integrates the oscillator signal, comparison circuitry that detects abnormal states, and a reset generator that responds to detected faults, thereby continuously adjusting the system state based on real-time oscillator performance.
2Speed
If component values are reduced for faster startup, then startup speed improves, but component variation errors increase
Solution Approach 1:
The patent applies self-service by designing a watchdog circuit that autonomously monitors and corrects RC oscillator failures without requiring external intervention. The circuit uses the oscillator's own output signal as its monitoring input, and when a fault is detected, it automatically generates a reset signal that corrects the oscillator state, enabling the system to self-diagnose and self-correct component variation errors.
Solution Approach 2:
The patent implements parameter changes by dynamically monitoring the voltage level and transition timing of the RC oscillator output signal. The watchdog circuit measures parameters such as the capacitive node voltage, transition duration, and signal frequency, comparing these against expected ranges to detect when component variations have caused the oscillator to malfunction, thereby adapting the system response based on real-time parameter analysis.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively detects and corrects faults in the RC oscillator, ensuring the generation of a proper clock signal and successful startup operations of the SoC by identifying and addressing stuck states in the oscillator.
Implementation Method 1
A watchdog circuit is introduced that includes a capacitive node, charge circuitry configured to selectively charge the capacitive node based upon the logic output signal
Implementation Method 2
discharge circuitry configured to selectively discharge the capacitive node based upon the logic output signal
Data Source
AI summary
An RC oscillator generates a periodic trigger signal, and a clock generator generates clock edges in response. A stuck-at-fault detection circuit detects a stuck-at-logic state of the periodic trigger signal and causes the RC oscillator to reset and causes a change in logic state of the periodic trigger signal. The RC oscillator includes first and second comparison circuits, a logic circuit receiving output from the first and second comparison circuits and generating the periodic trigger signal, and a clock generation circuit generating a clock signal therefrom. The stuck-at-fault detection circuit includes a capacitive node, charge circuitry charging the capacitive node based upon the periodic trigger signal, discharge circuitry discharging the capacitive node based upon the periodic trigger signal, and triggering circuitry asserting a reset signal to cause the RC oscillator to reset when the charge on the capacitive node indicates a stuck-at-logic state of the periodic trigger signal.