RC Oscillator Watchdog Reset for Stuck Startup Clocks
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Solution Overview
Problem
Standard RC oscillators can become stuck due to component variation errors, leading to failure in generating a clock signal for System on a Chip (SoC) startup, resulting in startup operation failures.
Innovation Solution
A fault detection and reset circuit is introduced, comprising a multiplexer, comparison circuits, and logic and control circuits to monitor capacitor voltages and generate a reset signal when faulty operation is detected, ensuring proper operation and resetting the RC oscillator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If an RC oscillator is used to provide a clock signal for SoC startup, then the startup time is reduced to microseconds, but the oscillator may become stuck due to component variation errors, causing startup failure
Solution Approach 1:
The patent implements a feedback mechanism where the output of the SR flip-flop is fed back to control the switching of capacitors. The Q and Qbar outputs control switches that connect capacitors to charge or discharge paths, creating a self-sustaining oscillation loop. This feedback ensures continuous oscillation unless a fault occurs, maintaining reliable clock generation during startup.
Solution Approach 2:
The patent incorporates a watchdog circuit that proactively monitors the oscillation state before startup failure occurs. The circuit preemptively detects stuck conditions by checking whether capacitors are charging/discharging as expected, and can trigger a reset before the SoC startup process fails, preventing the harmful outcome.
2Ease of manufacture
If the RC oscillator components are formed with standard manufacturing processes, then manufacturing cost is reduced, but component variation causes oscillation errors and startup failure
Solution Approach 1:
The patent uses asymmetric capacitor switching arrangements where different capacitors are connected to different switches (S1, S2, S3, S4) based on the flip-flop state. This asymmetric configuration ensures that at least one capacitor is always in a known state (charging or discharging), making the oscillation behavior predictable despite component variations. The asymmetric design compensates for manufacturing tolerances in individual components.
Solution Approach 2:
The patent dynamically changes the effective capacitance values by switching capacitors in and out of the circuit based on the oscillation phase. The watchdog circuit monitors voltage thresholds and timing parameters to detect deviations caused by component variations. By actively adjusting and monitoring operating parameters rather than relying on fixed precise component values, the system maintains reliability despite manufacturing variations.
3Reliability
If a watchdog circuit is added to detect oscillator faults, then startup reliability is improved, but the device complexity increases
Solution Approach 1:
The watchdog circuit components serve multiple functions: the same comparators and switches used for oscillation generation are also used for fault detection. The SR flip-flop both generates the clock signal and controls the capacitor switching for watchdog monitoring. This multi-functionality reduces the need for separate dedicated watchdog components, minimizing the increase in device complexity while maintaining improved reliability.
Solution Approach 2:
The patent merges the oscillation generation circuit and the fault detection circuit into a single integrated system. The capacitor charging/discharging paths serve both to generate the clock signal and to provide test signals for the watchdog comparators. The switches control both the oscillation phase and the watchdog monitoring simultaneously. This merging reduces overall circuit complexity compared to having separate independent watchdog circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit effectively detects faults in RC oscillators and triggers a reset, ensuring the generation of a proper clock signal for SoC startup, thereby preventing startup failures.
Implementation Method 1
a first capacitor (603) coupled between a first node (604) and ground, wherein the first node provides a first voltage (V1), and a second capacitor (605) coupled between a second node (606) and ground, wherein the second node provides a second voltage (V2)
Implementation Method 2
A first comparison circuit (620, 630) is enabled when a comparator enable signal is asserted and configured to assert its output when the first voltage becomes equal to a reference voltage, and a second comparison circuit is enabled when the comparator enable signal is deasserted and configured to assert its output when the second voltage becomes equal to the reference voltage
Data Source
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AI summary
An RC oscillator (fig. 3: 6) generates a periodic trigger signal (fig. 3, 4: Sc), and a clock generator (fig. 3: 22) generates clock edges in response (fig. 3: CLK2). A stuck-at-fault detection circuit (fig. 3, 4: 100) detects a stuck-at-logic state (fig. 3, 4, 5: SC fixe at 1) of the periodic trigger signal and causes the RC oscillator to reset (fig. 3: 100 out, fig. 4: ClkMon_Stop_B ) and causes a change in logic state of the periodic trigger signal (fig. 3, 4, 5: Sc at 0). The RC oscillator (fig. 3: 6) includes first and second comparison circuits (fig. 3: 80, 81), a logic circuit (fig. 3: 84) receiving output from the first and second comparison circuits and generating the periodic trigger signal (Sc), and a clock generation circuit (fig. 3, 4: 100) generating a clock signal therefrom (fig. 3: CLK2). The stuck-at-fault detection circuit (fig. 3, 4: 100) includes a capacitive node (Cap Node), charge circuitry (102, M1, M2) charging the capacitive node based upon the periodic trigger signal (Sc), discharge circuitry (102, M4, M5) discharging the capacitive node based upon the periodic trigger signal (Sc), and triggering circuitry (104, 106, 108, 110, 112) asserting a reset signal (ClkMon_Stop_B) to cause the RC oscillator to reset when the charge on the capacitive node (Cap_Node) indicates a stuck-at-logic state of the periodic trigger signal (Sc).