RC Power-On Reset Pulse Circuit With Low Power and Small Area
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Solution Overview
Problem
Existing power-on reset circuits face challenges in achieving low power consumption and small chip area occupancy while being able to generate reset signals for both short and long power-on reset delays, with existing solutions either having high power consumption or complex circuit structures.
Innovation Solution
A low-power pulse output circuit comprising PMOS and NMOS transistors, adjustable resistor and capacitor regulation modules, an inverter, and a buffer, which allows for adjustable resistance and capacitance to control power-on detection threshold and reset delay, eliminating the need for a high-precision reference source and comparator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If a reference circuit and active comparator circuit are used to generate reference voltage and compare power-on detection threshold, then controllable reset time is achieved, but power consumption increases and circuit structure becomes complex
Solution Approach 1:
The patent extracts and removes the reference circuit and active comparator circuit from the power-on reset circuit, retaining only the essential voltage division and detection functions. This elimination of unnecessary components directly reduces power consumption while maintaining the core functionality of generating controllable reset delays through passive RC time constants.
Solution Approach 2:
The patent replaces expensive, power-consuming active components (comparator circuit) with simple, low-cost passive components (resistors and capacitors). The RC time constant approach uses inexpensive passive elements to achieve the same timing function without the ongoing power consumption of active comparison circuits.
2Duration of action of moving object
If a reference circuit and active comparator circuit are used to generate reference voltage and compare power-on detection threshold, then controllable reset time is achieved, but circuit structure becomes complex and chip area increases
Solution Approach 1:
The patent extracts and removes the reference circuit and active comparator circuit from the power-on reset circuit, retaining only the essential voltage division and detection functions. This elimination of unnecessary components directly reduces power consumption while maintaining the core functionality of generating controllable reset delays through passive RC time constants.
Solution Approach 2:
The patent replaces expensive, power-consuming active components (comparator circuit) with simple, low-cost passive components (resistors and capacitors). The RC time constant approach uses inexpensive passive elements to achieve the same timing function without the ongoing power consumption of active comparison circuits.
3Area of stationary object
If NMOS transistors connected in series are used for voltage division, then chip area is reduced and operating current is decreased, but reset delay is too short (μs-level) for applications requiring longer delays
Solution Approach 1:
The patent introduces adjustable RC time constant elements that allow dynamic adjustment of the reset delay period. By making the resistance and capacitance values可调 (adjustable), the circuit can adapt to different timing requirements, transforming from a fixed μs-level delay to a configurable delay that can accommodate both short and long reset requirements.
Solution Approach 2:
The patent changes the key parameters (resistance and capacitance values) of the voltage division and timing circuits to achieve different reset delay characteristics. By adjusting these parameters, the circuit can maintain small chip area while achieving variable reset delays beyond the fixed μs-level limitation of series NMOS configurations.
Data Source
AI summary
A low-power pulse output circuit comprises first to third PMOS transistors, first NMOS to third NMOS transistors, a resistor regulation module, a capacitor regulation module, an inverter and a buffer. Drains of the first PMOS and first NMOS transistors, gates of the first NMOS, second PMOS, second NMOS, and third NMOS transistors are connected. Drain of the second PMOS transistor, gate of the third PMOS transistor and one terminal of the resistor regulation module are connected. The other terminal of the resistor regulation module and drain of the second NMOS transistor are connected. Drain of the third PMOS transistor, drain of the third NMOS transistor and an input terminal of the inverter are connected. An output terminal of the inverter, the other terminal of the capacitor regulation module and an input terminal of the buffer are connected.