RC Triggered ESD Protection Using Native NMOS Pseudo Resistor
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Solution Overview
Problem
RC triggered ESD protection circuits in semiconductor technology face challenges in setting the correct RC time constant to avoid false triggering and leakage current during normal power up, leading to unnecessary power losses.
Innovation Solution
Incorporating a native NMOS transistor with a low threshold voltage as a weak pull-up resistor in the trigger circuit, along with PMOS transistors, to form a pseudo resistor and capacitor, which adjusts the time constant to differentiate between ESD spikes and normal power up events, preventing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the RC time constant is set to detect ESD spikes, then ESD protection is improved, but leakage current occurs during normal power up
Solution Approach 1:
The patent uses a native NMOS transistor with threshold voltage that dynamically changes based on the voltage at its source terminal. During normal power-up, the threshold voltage remains high keeping the transistor off. During ESD events, the threshold voltage dynamically adjusts to enable proper detection while preventing false triggering, thus resolving the contradiction between ESD protection and leakage current.
Solution Approach 2:
The patent exploits the voltage-dependent threshold voltage parameter of the native NMOS transistor. The threshold voltage changes from a higher value during normal operation to a lower value during ESD events, enabling the circuit to differentiate between normal power-up and ESD spikes. This parameter change allows the circuit to maintain reliability while minimizing energy loss.
2Loss of energy
If the RC time constant is reduced to prevent leakage during power up, then power consumption is improved, but false triggering occurs during ESD events
Solution Approach 1:
The native NMOS transistor provides dynamic threshold voltage adjustment based on operating conditions. During ESD events, the rapid voltage change causes the threshold voltage to shift, enabling the circuit to maintain proper detection sensitivity even with reduced RC time constant, thus preventing false triggering while maintaining ESD detection accuracy.
3Speed
If a strong pull-up resistor is used in the trigger circuit, then the discharge transistor turns on faster, but leakage current increases during normal operation
Solution Approach 1:
The native NMOS transistor acts as a voltage-controlled resistance that dynamically adjusts its conductivity. During ESD events, the rapid voltage change causes the transistor to conduct strongly, providing fast discharge transistor turn-on. During normal operation, the transistor remains in a high-resistance state, minimizing leakage current. This dynamic behavior resolves the contradiction between speed and energy loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures the discharge transistor remains off during normal power up, reducing leakage current and power consumption while effectively clamping ESD voltage spikes, thereby enhancing ESD protection without false triggering.
Implementation Method 1
Incorporating a native NMOS transistor with a low threshold voltage as a weak pull-up resistor in the trigger circuit
Implementation Method 2
the time constant formed by the resistance element and the capacitance element is so chosen that the discharge transistor is turned off when the ESD protection device operates in a normal power up mode
Implementation Method 3
The turn-on of the discharge transistor may provide a bypass of the ESD current from the power bus to ground so as to clamp the voltage of the power bus to a level below the maximum rating voltage
Data Source
AI summary
An RC triggered ESD protection device comprises a discharge transistor, a driver circuit and a trigger circuit. The trigger circuit comprises a plurality of native NMOS transistors connected in parallel with a plurality of PMOS transistors operating as resistors. The relatively small resistance of the plurality of native NMOS transistors helps to keep a stable RC time constant value so that the ESD protection device can avoid a leakage current during a power up operation.