RCD-Based BCOM Bus Training for Faster DIMM Bring-Up
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Solution Overview
Problem
The existing memory controller involvement in BCOM training for DIMMs leads to inefficient use of the data bus during training, prolonging the DIMM bring-up time and complicating the memory controller design due to the integration of training intelligence and control logic.
Innovation Solution
Integrating BCOM training intelligence and control logic into the RCD and data buffers, utilizing a sideband I3C bus for communication, allowing the memory controller to be excluded from the training process, enabling parallel training of multiple BCOM busses and reducing the data bus usage during training.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller is involved in BCOM training, then the training process can be coordinated centrally, but the data bus usage increases and DIMM bring-up time is prolonged
Solution Approach 1:
The patent extracts the BCOM training intelligence and control logic from the memory controller and relocates it to the RCD and data buffers. This extraction allows the training process to occur independently within the memory module, eliminating the need for memory controller involvement during training and thereby reducing DIMM bring-up time without sacrificing training coordination capability.
Solution Approach 2:
The patent segments the training process into independent components within the memory module itself, specifically placing training intelligence in the RCD and data buffers. This segmentation enables the training to proceed in parallel with other memory operations and eliminates the sequential dependency on memory controller availability, thus reducing overall bring-up time.
2Reliability
If the memory controller integrates training intelligence and control logic, then centralized control is achieved, but the memory controller design becomes more complex
Solution Approach 1:
The patent extracts training intelligence and control logic from the memory controller to the RCD and data buffers. This extraction simplifies the memory controller design by removing the training functionality, reducing its complexity while maintaining reliable training control through the distributed intelligence in the RCD and data buffers.
3Reliability
If the data bus is used extensively during training, then training coordination is possible, but training efficiency decreases due to prolonged data bus occupancy
Solution Approach 1:
The patent extracts the training coordination functionality from the data bus-dependent memory controller and embeds it within the memory module's RCD and data buffers. This extraction enables training to proceed using local resources rather than requiring extensive data bus usage, thereby improving training efficiency while maintaining coordination reliability.
Data Source
AI summary
An apparatus is described. The apparatus includes a register clock redriver (RCD) chip comprising a buffer communication (BCOM) interface, a BCOM training control circuit and BCOM training control register space, the BCOM training control circuit is to: transmit a series of symbol transmissions over the BCOM interface to a data buffer with different respective clock phase delays to sweep the symbol transmissions within an eye window; collect resultants of the symbol transmissions from the data buffer; and, perform an analysis on the resultants to determine an appropriate clock phase within the eye window.