Resistance Change Memory Sidewall Bit Line Formation
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Solution Overview
Problem
The existing resistance change memory technologies face challenges in miniaturizing memory cells and reducing manufacturing costs due to the requirement of multiple lithography processes for forming bit lines and vias, which limits the size reduction and increases costs.
Innovation Solution
The proposed solution involves forming bit lines in a self-aligned manner using sidewall conductive layers and damascene technology, eliminating the need for additional lithography processes, thereby reducing the size of memory cells and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple lithography processes are used to form bit lines and vias, then manufacturing precision is maintained, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the formation of bit lines and vias into a single lithography process by using a shared conductive layer that serves both functions. The bit line conductive layer is formed in the same lithography step as the via conductive layer, merging two previously separate processes into one, thereby reducing process complexity while maintaining manufacturing precision.
Solution Approach 2:
The conductive layer formed by the lithography process serves multiple functions: it forms both the bit lines and the vias simultaneously. This multi-functional approach allows a single lithography process to accomplish what previously required multiple separate processes, reducing overall device complexity without sacrificing precision.
2Ease of operation
If traditional memory cell structure with selection transistor is used, then data read and write functionality is achieved, but memory cell size cannot be reduced below constant value
Solution Approach 1:
The patent extracts and removes the selection transistor from the memory cell structure, leaving only the essential resistance change element. This extraction eliminates the need for complex transistor gating mechanisms while maintaining data read and write capabilities through alternative selection methods, thereby enabling significant memory cell size reduction.
Solution Approach 2:
Instead of using a transistor to control current flow through the resistance change element, the patent inverts the approach by using the resistance change element itself as the primary control mechanism. The selection is achieved through bit line voltage control rather than transistor gating, fundamentally changing the operational paradigm to enable smaller cell sizes.
3Manufacturing precision
If bit line and via are formed by separate lithography processes, then manufacturing precision is maintained, but productivity decreases due to multiple processing steps
Solution Approach 1:
The patent merges the formation of bit lines and vias into a single lithography and deposition sequence. By forming both structures in one continuous process flow using the same lithography pattern, the number of discrete manufacturing steps is reduced, thereby increasing productivity while maintaining the precision required for proper structural formation.
Data Source
AI summary
According to one embodiment, a resistance change memory includes resistance change elements arrayed with a first space in a first direction and with a second space wider than the first space in a second direction orthogonal to the first direction, second conductive layers disposed on sidewalls of the resistance change elements, each of the second conductive layers having a width greater than or equal to a half of the first space in the first direction and having a width less than a half of the second space in the second direction, the second conductive layers functioning as a first bit line extending in the first direction, a second insulating layer disposed on a sidewall of the first bit line, and not filling the second space, and a third conductive layer functioning as a second bit line extending in the first direction by filling the second space.