RDL Air Cavity Structure for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of semiconductor devices leads to increased parasitic capacitance, which can adversely affect the operation performance despite efforts to reduce it by shortening metal routings.
Innovation Solution
The introduction of an air cavity between the patterned conductive layers in the semiconductor device design, which is formed by removing a sacrificial pattern from the dielectric layer, effectively reduces parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If metal routings are shortened to reduce parasitic capacitance, then parasitic capacitance is reduced, but operation performance is adversely affected
Solution Approach 1:
The patent changes the physical parameter of the dielectric material by introducing an air cavity (air gap) between the interconnection structure and the RDL. This parameter change reduces the parasitic capacitance without requiring shortening of metal routings, thereby maintaining operation performance while eliminating the harmful parasitic capacitance effect.
2Volume of moving object
If device size is reduced for miniaturization, then semiconductor device size is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by introducing an air cavity at a specific location between the interconnection structure and the RDL. This localized modification creates a region with different dielectric properties (air instead of solid dielectric), which reduces parasitic capacitance in that specific area without affecting the overall miniaturization of the device.
3Object-affected harmful factors
If air cavity is introduced to reduce parasitic capacitance, then parasitic capacitance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the sacrificial pattern before depositing the RDL. The sacrificial pattern is created in advance on the first dielectric layer, then the RDL is deposited over it, and finally the sacrificial pattern is removed to create the air cavity. This sequence of preliminary actions simplifies the overall manufacturing process by preparing the structure before final assembly.
Data Source
AI summary
The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing an interconnection structure. The method also includes forming a first dielectric layer on the interconnection structure. The method further includes forming a sacrificial pattern on the first dielectric layer. The method also includes forming an RDL on the first dielectric layer and the sacrificial pattern. The method further includes removing the sacrificial pattern to form an air cavity within the RDL.