Redistribution Layer Alignment in Stacked Dies for Shorter Interconnects
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Solution Overview
Problem
The challenge in semiconductor package design is to reduce interconnect lengths to minimize ohmic loss, heat generation, and signal delay, particularly in complex packages with multiple stacked dies, where precise alignment and redistribution layers are crucial.
Innovation Solution
The implementation of alignment marks with detailed features on semiconductor dies allows for precise measurement and correction of placement errors, enabling the formation of redistribution layers with improved accuracy, thereby reducing overlay errors to less than 0.5 microns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor packages use vertically stacked dies to reduce package size, then package density improves, but alignment precision deteriorates due to cumulative placement errors
Solution Approach 1:
Alignment marks are formed on the semiconductor dies before the stacking process. These marks serve as reference features that enable subsequent measurement and correction of placement errors, allowing the system to pre-establish a basis for precision correction rather than attempting to achieve perfect alignment directly during assembly
Solution Approach 2:
The system measures the actual positions of alignment marks on stacked dies and uses this measurement feedback to determine and apply correction values. This closed-loop approach allows the system to detect placement errors and compensate for them by adjusting the positioning of redistribution layers in subsequent processing steps
2Reliability
If interconnect lengths are reduced to minimize ohmic loss and signal delay, then electrical performance improves, but manufacturing complexity increases due to tighter alignment tolerances
Solution Approach 1:
The system replaces purely mechanical alignment methods with a measurement and correction approach. Instead of relying solely on mechanical precision of placement equipment, the invention uses optical or imaging systems to measure alignment mark positions and computationally determines correction values, substituting mechanical precision requirements with measurement and data processing
3Measurement precision
If alignment marks with detailed features are used to improve measurement precision, then placement accuracy improves, but device complexity increases
Solution Approach 1:
The alignment mark is segmented into multiple distinct features or elements with specific geometric relationships. This segmentation allows the measurement system to detect multiple reference points and calculate precise positional and rotational deviations, enabling accurate measurement while keeping each individual feature element relatively simple
Data Source
AI summary
An embodiment semiconductor package structure may include a first redistribution layer and a first semiconductor die attached to the first redistribution layer. The first semiconductor die may include first front-side electrical contacts and first back-side electrical contacts such that the first front-side electrical contacts are electrically connected to the first redistribution layer. The semiconductor package structure may further include a second redistribution layer formed over the first semiconductor die such that the second redistribution layer is electrically connected to the first back-side electrical contacts of the first semiconductor die and to a second semiconductor die attached to the second redistribution layer and positioned vertically over the first semiconductor die. The first semiconductor die may include at least two alignment marks separated by at least 50 microns. An overlay error between alignment of the first semiconductor die and the second redistribution layer may be less than or equal to 0.5 microns.