Redistribution Layer Routing for BGA Substrate Cost Reduction

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Solution Overview

Problem

Conventional integrated circuit (IC) packages, such as ball grid array (BGA) packages, face challenges in routing signals due to the complexity of substrate trace design, leading to increased costs associated with adding more layers to facilitate connections between bond pads and external package connections.

Innovation Solution

The implementation of a redistribution layer (RDL) on the integrated circuit chip to electrically connect bond pads and external package connections, reducing the number of layers required in the substrate and thereby lowering production costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the number of substrate layers is increased to facilitate signal routing between bond pads and external connections, then the routing capability is improved, but the manufacturing cost increases

Engineering Contradiction:
Improverouting capabilityVSAvoidmanufacturing cost
Core Design Contradiction:
Ease of operationVSEase of manufacture

Solution Approach 1:

The patent introduces a redistribution layer that extends the routing path from the front surface of the chip to the back surface, utilizing the third dimension (depth/vertical direction) to create additional routing pathways without adding horizontal substrate layers. This dimensional transition allows signals to be routed around obstacles and across the chip in a cost-effective manner.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The redistribution layer is embedded within the existing chip structure, nesting the routing functionality inside the chip body rather than adding external substrate layers. The conductive paths are formed within the chip's internal structure, utilizing the existing chip volume for routing purposes.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If the number of substrate layers is increased to complete trace routing, then the connection completeness is improved, but the device complexity increases

Engineering Contradiction:
Improveconnection completenessVSAvoidsubstrate layer complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the routing function from the substrate layers and relocates it to the chip's redistribution layer. By separating the routing functionality from the substrate structure, the substrate can maintain a simpler multi-layer configuration while the chip handles the complex routing internally through its redistribution layer.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The redistribution layer acts as an intermediary between the bond pads on the front surface and the external connections on the back surface. It provides a intermediate routing path that connects these two interfaces without requiring complex substrate trace routing, thereby simplifying the overall package structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9252119B1Ball grid array including redistribution layer, packaged integrated circuit including the same, and methods of making and using the same
Publication Date: 2016.02.02 MARVELL ASIA PTE LTD
  • US9252119B1 patent drawing
  • US9252119B1 patent drawing
  • US9252119B1 patent drawing

AI summary

Method, algorithms, architectures, packages, circuits, and/or approaches for relatively low cost packaged integrated circuits (e.g., ball grid array or BGA packages) are disclosed. For example, a packaged integrated circuit can include a first chip, the first chip including a plurality of bond pads; a plurality of bond pad connectors in electrical communication with the plurality of bond pads; a substrate having a plurality of layers, at least one of the plurality of layers being configured to electrically connect the plurality of bond pad connectors and a plurality of external package connections; and a redistribution layer on the first chip, wherein the redistribution layer is configured to electrically connect at least one of the plurality of bond pad connectors and at least one of the plurality of bond pads on the first chip.