Multi-Die RDL Assembly for Direct Board Attach Pitch Conversion

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Solution Overview

Problem

Current techniques for coupling integrated circuit devices directly to circuit boards are limited by manufacturing constraints, device size, and interconnect congestion, leading to increased costs and implementation challenges.

Innovation Solution

The implementation of a microelectronic assembly that includes a first redistribution layer (RDL) with specific conductive pathways, conductive pillars, and a second RDL, allowing for direct electrical coupling of multiple IC dies to a circuit board without a package substrate, thereby addressing interconnect pitch variance and reducing package thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If current techniques are used to couple integrated circuit devices directly to circuit boards, then manufacturing constraints and device size limitations are encountered, but this leads to increased costs and implementation challenges

Engineering Contradiction:
Improvemanufacturing constraintVSAvoidimplementation challenge
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent introduces a redistribution layer (RDL) as an intermediary structure between the IC die and the circuit board. The RDL includes conductive pathways and conductive contacts that mediate the connection, allowing pitch conversion and direct attachment without requiring a traditional package substrate. This intermediary structure resolves the manufacturing constraints by enabling direct board attachment while managing interconnect complexity through the RDL's pitch transformation capabilities.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Length of stationary object

If direct attachment of multi-die IC packages to circuit boards is implemented, then package thickness is reduced and design flexibility is improved, but interconnect congestion and pitch variance issues arise

Engineering Contradiction:
Improvepackage thicknessVSAvoidinterconnect congestion
Core Design Contradiction:
Length of stationary objectVSDevice complexity

Solution Approach 1:

The patent changes the pitch parameter of conductive interconnects through the redistribution layer. The first RDL has a first pitch suitable for die-level interconnects, while the second RDL has a second pitch suitable for circuit board-level interconnects. This parameter transformation allows direct attachment with reduced package thickness while managing interconnect congestion by matching pitch requirements at different hierarchical levels.

Inventive Principle:
Principle #35Parameter changes

3Speed

If multiple IC dies are coupled directly to a circuit board, then power delivery and signal speed are improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvesignal speedVSAvoidalignment precision
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent segments the interconnect structure into multiple functional layers: the first RDL with first conductive contacts for die attachment, the second RDL with second conductive contacts for board attachment, and conductive pillars for vertical interconnection. This segmentation allows each layer to be optimized for its specific function and pitch requirement, improving signal speed while distributing the manufacturing precision requirements across multiple manufacturable stages rather than requiring single-step ultra-precise alignment.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12347782B2Microelectronic assemblies with direct attach to circuit boards
Publication Date: 2025.07.01 INTEL CORP
  • US12347782B2 patent drawing
  • US12347782B2 patent drawing
  • US12347782B2 patent drawing

AI summary

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first redistribution layer (RDL), having a first surface with first conductive contacts having a first pitch between 170 microns and 400 microns, an opposing second surface, and first conductive pathways between the first and second surfaces; a first die and a conductive pillar in a first layer on the first RDL; a second RDL on the first layer, the second RDL having a first surface, an opposing second surface with second conductive contacts having a second pitch between 18 microns and 150 microns, and second conductive pathways between the first and second surfaces; and a second die, in a second layer on the second RDL, electrically coupled to the first conductive contacts via the first conductive pathways, the conductive pillar, the second conductive pathways, and the second conductive contacts.