RDL Bump Integration Structure for Delamination-Resistant Openings
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Solution Overview
Problem
In high-density integrated circuits, the parasitic capacitance between metal lines leads to RC delay and cross-talk, which is not effectively reduced by existing low-k dielectric materials, and the formation of conductive bumps is hindered by delamination and stress issues at the interface between passivation and dielectric layers.
Innovation Solution
The formation of pulled-in or lined-up openings in the dielectric layer over conductive features enhances adhesion and reduces stress between passivation and dielectric layers, preventing delamination and improving seed layer step coverage, thereby increasing the reliability and yield of conductive bump formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-k dielectric materials are employed to reduce parasitic capacitance, then RC delay and cross-talk are reduced, but delamination and stress issues occur at the interface between passivation and dielectric layers
Solution Approach 1:
A buffer layer is introduced between the low-k dielectric layer and the passivation layer to serve as an intermediary that reduces stress concentration and prevents delamination. This buffer layer absorbs the mechanical stress generated by the low-k dielectric material while maintaining the electrical performance benefits of reduced parasitic capacitance.
Solution Approach 2:
The mechanical properties of the dielectric structure are modified by changing the material composition and thickness parameters of the buffer layer. By adjusting these parameters, the stress distribution is optimized to prevent delamination while preserving the low-k dielectric's ability to reduce RC delay and cross-talk.
2Ease of manufacture
If conventional opening formation processes are used, then manufacturing simplicity is maintained, but seed layer step coverage is poor and bump formation reliability is reduced
Solution Approach 1:
The buffer layer is formed in advance before the opening formation process. This preliminary action prepares the surface geometry to ensure proper seed layer deposition by creating a more favorable step coverage profile, which improves bump formation reliability without adding complex steps to the overall manufacturing process.
Data Source
AI summary
A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.