Redistribution-Layer Chip Stacking Without TSVs in 3D Packaging
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Solution Overview
Problem
The high technological requirements and high cost associated with Through Silicon Vias (TSVs) in advanced 3D packaging processes hinder the efficient and cost-effective implementation of high-density electrical interconnections in semiconductor packages.
Innovation Solution
A semiconductor packaging method involving Flip-Chip mounting of semiconductor devices on redistribution layers, eliminating the need for TSVs, and using stacked interconnections through redistribution layers and connection structures to achieve high-density electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Through Silicon Vias (TSVs) are used to form high-density electrical interconnections in advanced 3D packaging, then the electrical connection density is improved, but the technological complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent divides the interconnection structure into multiple segments: redistribution layers (RDLs) on different planes, connection structures (such as bumps or vias) for vertical connections, and molding layers for encapsulation. This segmentation allows high-density interconnections to be achieved through planar redistribution rather than requiring complex through-silicon vias, thereby reducing manufacturing complexity while maintaining connection density
Solution Approach 2:
The patent transitions from three-dimensional Through Silicon Via structures to a more planar, two-dimensional redistribution layer approach. By spreading connections across multiple RDL planes and using surface-mounted connection structures, the patent achieves high-density interconnections without the need for deep vertical penetration through the substrate, thus reducing technological complexity
2Productivity
If Through Silicon Vias (TSVs) are used to achieve high-density electrical interconnections, then the interconnection capability is improved, but the manufacturing cost increases
Solution Approach 1:
The patent employs standard semiconductor manufacturing processes and materials for creating redistribution layers and connection structures, replacing the expensive and specialized TSV process. The use of conventional RDL fabrication techniques and standard bonding methods makes the manufacturing process more cost-effective while achieving the same interconnection capability
3Ease of manufacture
If conventional packaging structures are used, then the manufacturing process is simpler, but the high-density electrical interconnections between chips cannot be achieved
Solution Approach 1:
The patent merges multiple functions into the redistribution layer structure: electrical interconnection, signal routing, and mechanical support. By integrating these functions into the RDL architecture rather than using separate TSV structures, the patent achieves high-density interconnections with a manufacturing process that remains relatively simple and compatible with conventional semiconductor fabrication
Data Source
AI summary
The present disclosure relates to a semiconductor packaging method, a semiconductor assembly component and an electronic device in the technical field of semiconductor packaging, in which a first semiconductor device of a first packaged unit is Flip-Chip mounted on a first redistribution layer and is electrically connected to a second redistribution layer through the first redistribution layer and connection structures. A second semiconductor device of a second packaged unit is Flip-Chip mounted on a third redistribution layer and is electrically connected to connection terminals through the third redistribution layer. Stacked interconnection of the first semiconductor device and the second semiconductor device is realized by die-attaching the connection terminals and the second redistribution layer. Thus, no Through Silicon Via processes are needed, reducing the costs for die stacking.