RDL Package Contact Structure Without UBM for IMC Reliability

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Solution Overview

Problem

Conventional electronic device packages face limitations in line width/spacing (L/S) and thickness, leading to issues with the release of glass wafers during redistribution layer (RDL) formation, intermetallic compound (IMC) generation, and increased fabrication costs due to insufficient bottommost wiring layer thickness, necessitating additional under bump metallurgy (UBM).

Innovation Solution

The electronic device package design includes a first circuit layer with a dielectric layer having an aperture width that increases from the first surface to the second surface, allowing for a thicker electrical contact that omits the need for UBM, and a method of manufacturing involving a panel-level substrate with a conductive layer, where the panel-level substrate is released, and at least a portion of the conductive layer is removed to form an electrical contact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a conventional substrate with embedded circuit is used, then electronic components can be disposed and electrically connected, but the line width/spacing (L/S) cannot be reduced below certain limits

Engineering Contradiction:
Improveline width/spacingVSAvoidcircuit design flexibility
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The patent changes the fundamental parameter of the circuit carrier from a substrate with embedded circuits to a redistribution layer (RDL) structure formed on a glass wafer. This allows the L/S to be reduced significantly while maintaining electrical connectivity, as the RDL approach enables finer line widths and spacing compared to conventional substrate embedding techniques.

Inventive Principle:
Principle #35Parameter changes

2Length of stationary object

If the bottommost wiring layer thickness is insufficient, then the overall package thickness can be reduced, but intermetallic compound (IMC) may be generated during thermal processing, deteriorating reliability

Engineering Contradiction:
Improvepackage thicknessVSAvoidbonding reliability
Core Design Contradiction:
Length of stationary objectVSReliability

Solution Approach 1:

The patent applies preliminary action by forming an under bump metallurgy (UBM) layer in advance on the bottommost wiring layer before mounting solder balls. This UBM layer serves as a protective barrier that prevents IMC generation during subsequent thermal processes, thereby ensuring bonding reliability while allowing the overall package thickness to remain reduced.

Inventive Principle:
Principle #10Preliminary action

3Length of stationary object

If the bottommost wiring layer thickness is insufficient, then package thickness is reduced, but additional under bump metallurgy (UBM) is required, increasing fabrication costs

Engineering Contradiction:
Improvepackage thicknessVSAvoidfabrication cost
Core Design Contradiction:
Length of stationary objectVSEase of manufacture

Solution Approach 1:

The patent merges the bottommost wiring layer and the UBM layer into a integrated structure. The UBM layer is formed as part of the RDL fabrication process on the glass wafer, combining the functions of electrical connectivity and solder ball mounting protection. This integration reduces the need for separate manufacturing steps and materials, thereby lowering fabrication costs while maintaining the reduced package thickness.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11923285B2Electronic device package and method of manufacturing the same
Publication Date: 2024.03.05 ADVANCED SEMICON ENG INC
  • US11923285B2 patent drawing
  • US11923285B2 patent drawing
  • US11923285B2 patent drawing

AI summary

An electronic device package and a method for manufacturing the same are provided. The electronic device package includes a circuit layer and an electronic component. The circuit layer includes a dielectric layer having an opening, and an electrical contact. A width of an aperture of the opening increases from a first surface toward a second surface. The electrical contact is at least partially disposed in the opening and exposed through the opening. The electronic component is disposed on the second surface and electrically connected to the circuit layer.