RDL Copper Patterning for Fine-Pitch InFO Packaging

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The increasing miniaturization of semiconductor chips and the need for higher I/O pad density in smaller areas pose challenges for packaging, including limited I/O pad numbers due to pitch limitations and the risk of solder bridges.

Innovation Solution

The development of Integrated Fan-Out (InFO) packages and methods that utilize various processes such as PR-etching, HM-etching, and PR-assisted plating to form Redistribution Lines (RDLs) and conductive features, allowing for increased I/O pad density and reduced pitch without reliability issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the pitch of I/O pads is decreased to increase density, then the number of I/O pads per area increases, but solder bridges may occur reducing reliability

Engineering Contradiction:

Improvenumber of I/O padsVSAvoidsolder bridge risk

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from planar 2D pad arrangement to 3D vertical stacking with redistribution layers. Multiple conductive layers (RDL0, RDL1, etc.) are formed at different heights, allowing I/O pads to be redistributed in three dimensions. This vertical dimension enables higher pad density without reducing pitch, as pads can be routed to different layers to avoid conflicts and solder bridge risks.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the single-layer pad structure into multiple segmented conductive layers. Each RDL layer contains a subset of the total I/O pads, and pads are distributed across different layers and lateral positions. This segmentation allows the system to achieve higher overall density while maintaining adequate spacing within each layer, preventing solder bridges.

Inventive Principle:

Principle #1Segmentation

2Ease of manufacture

If photoresist is used for patterning conductive features, then manufacturing process is simplified, but photoresist collapsing occurs at reduced pitch

Engineering Contradiction:

Improvepatterning process simplicityVSAvoidminimum pitch

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent introduces a mandrel structure as an intermediary between the photoresist pattern and the final conductive feature. The photoresist is deposited on the mandrel, and the mandrel provides mechanical support that prevents photoresist collapse during subsequent processing. This intermediary enables patterning at reduced pitches while maintaining photoresist structural integrity.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The mandrel structure is formed in advance before photoresist deposition. This preliminary action creates a supportive framework that prevents photoresist collapse during the patterning process. The mandrel is prepared with appropriate dimensions and material properties to provide the necessary mechanical support for high-density patterning.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If fan-in packaging is used for small dies, then throughput is higher and cost is lower, but the number of I/O pads is limited by die area

Engineering Contradiction:

Improvepackaging throughputVSAvoidnumber of I/O pads

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent extends the I/O pad distribution from the 2D die surface into the 3D vertical space using multiple redistribution layers. Conductive features are formed at different heights (RDL0, RDL1, RDL2, etc.), effectively utilizing the vertical dimension to increase the total number of accessible I/O pads without increasing die area. This enables fan-in packaged dies to achieve higher I/O counts while maintaining the throughput and cost advantages of pre-saw packaging.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the formation of conductive features with reduced minimum pitch, enhancing I/O pad density and improving packaging efficiency without significantly increasing manufacturing costs or causing photoresist collapsing problems.

Implementation Method 1

etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer

Methodology Applied

Scientific EffectEtching:

Implementation Method 2

without significantly increasing manufacturing costs or causing photoresist collapsing problems

Methodology Applied

Scientific EffectPhotoresist collapsing resistance:

Data Source

PatentUS12315819B2Method of forming RDLs and structure formed thereof

Publication Date: 2025.05.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes encapsulating a device die in an encapsulating material, planarizing the device die and the encapsulating material, and forming a first plurality of conductive features electrically coupling to the device die. The step of forming the first plurality of conductive features includes a deposition-and-etching process, which includes depositing a blanket copper-containing layer, forming a patterned photo resist over the blanket copper-containing layer, and etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer.