RDL Dummy Line Layout for Semiconductor Surface Planarity
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and smaller package sizes for electronic components, requiring improved methods for fabricating semiconductor devices with better surface flatness and uniformity during the redistribution layer (RDL) process.
Innovation Solution
The method involves forming dummy redistribution lines with specific spacing and modification techniques to enhance the flatness of the polymer layer, followed by the formation of conductive connectors, which improves the topography and supports the formation of conductive bumps, ensuring a planar surface for efficient packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional RDL fabrication methods are used, then manufacturing process is simple, but surface flatness and uniformity of the polymer layer deteriorate
Solution Approach 1:
The patent applies preliminary action by forming dummy redistribution lines in the polymer layer before completing the RDL fabrication process. These dummy lines are strategically placed to pre-establish a uniform surface topology that compensates for potential flatness issues in subsequent processing steps, thereby improving surface flatness without requiring complex post-processing
2Productivity
If integration density is increased, then more components are integrated into given area, but package size reduction becomes more difficult
Solution Approach 1:
The patent applies parameter changes by modifying the physical and chemical parameters of the polymer layer through controlled formation of dummy redistribution lines. This changes the surface topology parameters (flatness, uniformity) of the polymer layer, which enables better planarization and supports higher integration density while maintaining manageable package sizes through improved surface control
Data Source
AI summary
A method for fabricating a semiconductor device is provided. The method includes generating a redistribution layer (RDL) layout, wherein the RDL layout comprises a plurality of redistribution lines; determining a first dummy region in the RDL layout according to the redistribution lines; disposing a plurality of first dummy redistribution lines in the first dummy region; performing a first modification process to enlarge at least one of the first dummy redistribution lines; determining the enlarged one of the first dummy redistribution lines as a second dummy region in the RDL layout when an area of the enlarged one of the first dummy redistribution lines is greater than a threshold value; disposing a plurality of second dummy redistribution lines in the second dummy region; and patterning a metal layer according to the RDL layout after disposing the second dummy redistribution lines in the second dummy region.