Redistribution Layer Layout With Dummy Lines for Surface Flatness
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to achieve high integration density and smaller package sizes while maintaining surface flatness and processability of redistribution layers (RDLs) in semiconductor devices.
Innovation Solution
The implementation of dummy redistribution lines and a controlled layout design method, including reverse tone and iterative modification processes, to optimize the spacing and configuration of redistribution lines, thereby improving the topography and facilitating the formation of conductive connectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the spacing between redistribution lines is reduced to increase integration density, then more components can be integrated into a given area, but the surface flatness of the polymer layer deteriorates
Solution Approach 1:
The patent applies preliminary action by inserting dummy redistribution lines into the layout design before the actual fabrication process. These dummy lines are strategically placed in regions where they will provide mechanical support to the polymer layer during subsequent bump formation processes, preventing surface depression without interfering with the functional circuit operation
Solution Approach 2:
The patent uses copying by creating dummy redistribution lines that replicate the structure and material composition of actual redistribution lines. These dummy lines are electrical isolates but structurally identical, allowing them to serve as structural support copies that mimic the mechanical properties of functional lines without creating electrical interference
2Area of stationary object
If the package size is reduced to meet smaller application requirements, then less area is utilized, but the processability of the redistribution layer deteriorates
Solution Approach 1:
The patent applies local quality by selectively placing dummy redistribution lines only in specific regions where structural support is needed, rather than uniformly across the entire package. This localized approach maintains package compactness while providing targeted support to polymer layers in critical areas during the bump formation process
Solution Approach 2:
The dummy redistribution lines serve as intermediaries between the functional circuit requirements and the packaging constraints. They mediate by providing the necessary structural support for manufacturability while occupying minimal space, thus enabling small package sizes without compromising processability
3Manufacturing precision
If dummy redistribution lines are added to improve surface flatness, then polymer layer uniformity is enhanced, but the layout complexity increases
Solution Approach 1:
The patent applies equipotentiality by designing the dummy redistribution lines to have the same structural properties and material composition as the functional redistribution lines. This creates a uniform structural environment across the package, ensuring consistent polymer layer formation and bump quality without introducing structural variations that would complicate the manufacturing process
Data Source
AI summary
A semiconductor device includes an interconnect structure, a passivation layer, and a redistribution layer. The passivation layer is over the interconnect structure. The redistribution layer is over the passivation layer. The redistribution layer comprises a redistribution pattern and at least one dummy redistribution line. The redistribution pattern is electrically connected with a metallization pattern of the interconnect structure. The at least one dummy redistribution line is electrically isolated from the metallization pattern of the interconnect structure. The dummy redistribution line extends along a first direction and has opposite first and second ends along the first direction, and the first and second ends of the dummy redistribution line are immediately adjacent the redistribution pattern.