Redistribution Layer Dummy Structures for Planarization

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Solution Overview

Problem

The redistribution layer (RDL) in packaging experiences surface fluctuations due to the pattern of metal traces, leading to electrical loss and process yield issues in the upper metal trace formation.

Innovation Solution

Incorporating dummy structures adjacent to conductive structures in the RDL, with controlled width and gap configurations, to enhance the degree of planarization of the dielectric layer, thereby improving the yield and reducing electrical loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a metal trace pattern is formed in the redistribution layer, then the electrical connection is established, but the dielectric layer surface becomes non-planar causing process failure and electrical loss

Engineering Contradiction:
Improveelectrical connectionVSAvoidsurface planarity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent introduces dummy structures (non-conductive or conductive) adjacent to the metal traces to create local variations in the redistribution layer. These dummy structures have different material properties or geometries than the metal traces, allowing them to fill in surface irregularities locally and provide a planar surface for subsequent dielectric coating without affecting the electrical function of the metal traces.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The dummy structures act as intermediary elements between the non-planar metal trace surface and the dielectric layer. By placing these intermediate structures around the metal traces, the patent creates a transition zone that smooths out surface variations and enables uniform dielectric deposition, thereby resolving the conflict between maintaining trace functionality and achieving surface planarity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If the dielectric layer is coated on a non-planar surface, then the redistribution layer is formed, but the upper metal trace formation fails and electrical loss occurs

Engineering Contradiction:
Improveredistribution layer formationVSAvoidprocess yield
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by forming dummy structures around the metal traces before coating the dielectric layer. This pre-preparation step creates a planarized surface in advance, ensuring that subsequent dielectric coating and upper metal trace formation processes can proceed without defects, thereby improving process yield and reducing electrical loss.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If dummy structures are added around conductive structures, then the degree of planarization is improved, but the device complexity increases

Engineering Contradiction:
Improvedegree of planarizationVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent optimizes parameters of the dummy structures, such as their width, spacing, and material composition, to achieve the required degree of planarization (greater than 95%) while minimizing their impact on overall device complexity. By carefully controlling these parameters, the dummy structures provide effective surface planarization without excessively increasing the number of components or manufacturing steps.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11251115B1Redistribution structure and forming method thereof
Publication Date: 2022.02.15 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11251115B1 patent drawing
  • US11251115B1 patent drawing
  • US11251115B1 patent drawing

AI summary

A redistribution structure including a first redistribution layer is provided. The first redistribution layer includes a dielectric layer; at least one conductive structure located in the dielectric layer, wherein the at least one conductive structure has a width L; and at least one dummy structure located adjacent to the at least one conductive structure and located in the dielectric layer, and the at least one dummy structure has a width D, wherein there is a gap width S between the at least one dummy structure and the at least one conductive structure, and a degree of planarization DOP of the first redistribution layer is greater than or equal to 95%, wherein DOP=[1−(h/T)]*100%, and h refers to a difference between a highest height and a lowest height of a top surface of the dielectric layer; and T refers to a thickness of the at least one conductive structure.