RDL Conductive Feature Etching to Eliminate Fine-Pitch Undercuts
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Solution Overview
Problem
The increasing miniaturization of semiconductor chips and the need for higher I/O pad density in semiconductor dies complicates packaging, leading to issues such as limited I/O pad numbers, solder bridges, and reduced yield due to fixed ball-size limitations in conventional packaging technologies.
Innovation Solution
A three-step etching process is employed to form semiconductor structures with reduced undercuts in redistribution layers (RDLs), enhancing the reliability of vias and metal lines by eliminating or reducing lateral dimensions through selective re-etching based on pitch thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional packaging technology is used with fixed ball-size requirements, then solder balls must have a certain size, but this limits the number of solder balls that can be packed on the surface of a die
Solution Approach 1:
The patent changes the size parameter of the solder balls to enable higher density packaging. By using smaller solder balls than conventional sizes, the invention allows more balls to be packed on the die surface, directly resolving the contradiction between ball size and number of balls.
Solution Approach 2:
The patent transitions from traditional two-dimensional packaging to three-dimensional packaging by stacking multiple layers of dies and solder balls vertically. This dimensional change allows significantly more solder balls to be packed without increasing the horizontal footprint, thereby increasing the quantity while maintaining compact size.
2Quantity of substance
If the pitch of the pads is decreased to increase I/O pad density, then more I/O pads can be packed, but solder bridges may occur
Solution Approach 1:
The patent resolves the solder bridge issue by transitioning to three-dimensional packaging with stacked layers. Instead of decreasing pitch in the same plane which causes solder bridges, the invention stacks solder balls and I/O pads in multiple vertical layers, maintaining adequate horizontal spacing while increasing total I/O pad density through the third dimension.
Solution Approach 2:
The patent segments the I/O pads and solder balls into multiple separate layers stacked vertically. This segmentation allows each layer to have sufficient spacing to prevent solder bridges, while the overall structure achieves high density through the stacking of multiple segments in the vertical dimension.
3Productivity
If fan-in packaging is used to maintain die size, then throughput is improved, but the number of I/O pads is limited due to pitch constraints
Solution Approach 1:
The patent resolves the I/O pad limitation in fan-in packaging by adding the vertical dimension through stacking. Multiple layers of dies and solder balls are stacked vertically, allowing the number of I/O pads to increase significantly while maintaining the same die size and benefiting from the high throughput of fan-in packaging processes.
Solution Approach 2:
The patent implements a nested structure where multiple layers of dies and solder balls are stacked one on top of another, with each layer containing complete I/O pad arrays. This nesting approach allows the system to pack more I/O pads within the same footprint by utilizing vertical space, thereby increasing capacity without sacrificing the throughput advantages of fan-in packaging.
4Ease of manufacture
If undercuts are present in redistribution layers, then manufacturing is simpler, but reliability of vias and metal lines is reduced
Solution Approach 1:
The patent applies a re-etching process that performs an additional etching step beyond the standard formation process. This excessive action partially removes the adhesion layer to eliminate undercuts, accepting the additional process step to achieve the reliability improvement. The selective re-etching targets only the problematic undercut regions without affecting the overall structure.
Data Source
AI summary
A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.