RDL-First Fan-Out Package Structure for High-Density 3D Stacking
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and efficient packaging of electronic components due to the limitations of existing packaging technologies, which require larger areas and are not suitable for high-bandwidth communications.
Innovation Solution
The implementation of a 'RDL-first' process for semiconductor packaging, involving the formation of redistribution structures before semiconductor devices are placed, allows for the creation of three-dimensional package structures with through integrated fan-out vias and conductive balls, enabling efficient electrical testing and stacking, thereby reducing area occupation and improving communication bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional packaging technologies are used, then manufacturing process is simpler, but area occupation is larger and integration density is lower
Solution Approach 1:
The patent implements a three-dimensional package structure by stacking multiple semiconductor devices vertically through through-vias that penetrate the molding material, transitioning from traditional two-dimensional planar packaging to three-dimensional vertical packaging. This dimensional change reduces area occupation while accommodating increased device integration density
Solution Approach 2:
The redistribution structures are formed prior to placing the semiconductor devices in the RDL-first process. This preliminary formation of conductive pathways enables subsequent vertical stacking and through-via integration, achieving compact three-dimensional packaging with reduced area footprint
2Quantity of substance
If device size is reduced for higher integration density, then more components fit in given area, but packaging becomes more difficult and area reduction is limited
Solution Approach 1:
The invention achieves higher integration density by utilizing the vertical dimension through stacked semiconductor devices connected by through-vias. This three-dimensional arrangement allows more components to be integrated within a smaller planar footprint by exploiting vertical space rather than merely reducing individual device dimensions
3Power
If conventional packaging is used, then manufacturing is easier, but communication bandwidth is insufficient for high-speed applications
Solution Approach 1:
The RDL-first process forms redistribution structures with multiple conductive layers and through-vias before device placement. This preliminary creation of complex interconnect pathways enables high-bandwidth communication by establishing multiple parallel signal routes and reducing signal trace lengths, which is essential for high-speed applications
Solution Approach 2:
The package structure is segmented into multiple functional layers including redistribution layers, dielectric layers, and through-vias that are stacked vertically. This segmentation creates multiple independent signal pathways that can operate in parallel, increasing overall communication bandwidth while managing structural complexity through modular layering
Data Source
AI summary
A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.