Redistribution Layer Geometry for Crack-Resistant IC Packages

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Solution Overview

Problem

Integrated circuit (IC) packages face reliability issues due to stress-induced cracks in redistribution layer (RDL) structures, which affect the performance and reliability of IC packages, especially under environmental stresses like moisture, pressure, and temperature.

Innovation Solution

The development of RDL structures with specific geometric configurations, including a cap region, a routing region, and an intermediate region with varying widths, which helps in distributing stress and preventing crack formation, is implemented. These structures are formed using conductive materials like copper or aluminum and are integrated into the IC package's insulating layers to enhance structural reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional RDL structures are used in IC packages, then manufacturing is simpler, but stress-induced cracks occur under environmental stresses

Engineering Contradiction:
Improvecrack resistanceVSAvoidRDL structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The RDL structure is divided into multiple distinct regions: a first region with a first width, a second region with a second width greater than the first width, and a third region with a third width less than the second width. This segmentation allows stress to be distributed across different width zones, preventing stress concentration that would lead to cracks at via interfaces.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the RDL structure have different widths tailored to specific functional requirements. The intermediate second region with greater width provides enhanced stress distribution capability at critical locations, while the first and third regions maintain narrower widths for routing efficiency. This local variation in geometry optimizes both reliability and electrical performance.

Inventive Principle:
Principle #3Local quality

2Reliability

If RDL structure with varying widths is implemented, then stress distribution improves, but manufacturing precision requirements increase

Engineering Contradiction:
Improvestress distributionVSAvoidwidth control precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The varying width configuration is designed and planned in advance during the structure formation process. The first, second, and third regions are intentionally created with different widths from the outset, allowing stress distribution to be built into the structure before environmental stresses are applied. This preliminary structural design eliminates the need for dynamic adjustments during operation.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If intermediate region with greater width is added, then crack prevention improves, but device complexity increases

Engineering Contradiction:
Improvecrack preventionVSAvoidRDL region count
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The RDL structure utilizes the lateral dimension by varying width across different regions rather than maintaining a uniform cross-section. The intermediate second region extends wider than the adjacent first and third regions, creating a stepped or tapered profile that enhances stress distribution. This dimensional variation adds crack prevention capability without requiring additional layers or vertical complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11848271B2Redistribution layer structures for integrated circuit package
Publication Date: 2023.12.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11848271B2 patent drawing
  • US11848271B2 patent drawing
  • US11848271B2 patent drawing

AI summary

A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.