High Density RDL Interconnect Bridge for Multi-Die IC Packages
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Solution Overview
Problem
Current integrated circuit (IC) packaging technologies face challenges in achieving high-density interconnects between multiple chips, leading to increased manufacturing costs and complexity, particularly due to the need for interposers and limited tolerances in die selection, which hinder efficient die-to-die interconnection and signal quality.
Innovation Solution
The proposed IC package design incorporates a reconstituted layer with encapsulating material, a first dielectric layer with vias, and a second dielectric layer featuring redistribution layers and bridge interconnects, eliminating the need for an interposer and allowing for high-density electrical connections between multiple dies, thereby enhancing manufacturing yield and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional IC packaging with interposers is used to achieve high-density interconnects between multiple chips, then signal quality between chips is improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent removes the interposer component from the packaging structure entirely. Instead of using an interposer to facilitate die-to-die interconnection, the invention directly connects multiple dies to the substrate through redistribution layers and vias, eliminating the intermediate component while maintaining signal quality and reducing complexity
Solution Approach 2:
The patent combines the functions of the interposer, redistribution layers, and interconnect structures into a integrated packaging approach. The substrate directly provides the interconnection functionality that was previously distributed across multiple components, merging the interposer's routing function with the substrate and RDL structures
2Adaptability or versatility
If interposers are used to enable die-to-die interconnection, then I/O interconnection is achieved, but manufacturing yield decreases due to limited tolerances in die selection
Solution Approach 1:
The patent changes the geometric parameters of the redistribution layers and via structures to accommodate variations in die dimensions and positions. By designing RDLs with appropriate trace widths, spacing, and via diameters that tolerate die selection variations, the system achieves high manufacturing yield while maintaining adaptability to different die configurations
Solution Approach 2:
The substrate and redistribution layer structure is designed to universally accommodate multiple dies with varying parameters. The RDL network provides flexible routing that can connect different die types and sizes to the same substrate interface, making the packaging system adaptable to various die selections without requiring precise tolerance matching
3Reliability
If high-density interconnects are implemented using traditional methods, then signal quality between multiple chips is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive interposer components with cost-effective redistribution layers formed through standard semiconductor fabrication processes. The RDLs use conventional metal layers and dielectric materials that are already part of the manufacturing stack, eliminating the need for costly interposer procurement and assembly while maintaining high-density interconnect capability
Solution Approach 2:
The patent replaces the mechanical assembly process of attaching dies to interposers with a more efficient wafer-level fabrication process. The redistribution layers and vias are formed using standard semiconductor manufacturing techniques such as photolithography, etching, and deposition, which are more cost-effective and scalable than manual or automated pick-and-place assembly of interposers
Data Source
AI summary
An integrated circuit (IC) package is disclosed that contains high density interconnects to connect multiple dies. The IC package includes an encapsulated layer, a first dielectric layer, and a second dielectric layer. The encapsulated layer forms the base of the IC package and includes the multiple dies. The first dielectric layer positioned between the encapsulated layer and the second layer. The first dielectric layer includes vias to connect to the input/output pads of active surfaces of the multiple dies. The second dielectric layer includes interconnect layers where at least one of the interconnect layers forms an electrical path to connect at least two of the multiple dies together. According to embodiments of the present disclosure, the IC package enables a high manufacturing yield due to large tolerances allowed for selection of dies. Embodiments of the present disclosure also increase an amount of input/output interconnection between multiple dies in the IC package. Embodiments of the present disclosure further enable lower manufacturing costs because of the use of mature reconstituted dies and redistribution layer technologies and the lack of a need for an interposer to connect multiple dies.