Semiconductor Package RDL Interconnect Eliminates Wire-Bond Parasitic Inductance
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Solution Overview
Problem
Wire-bonding in semiconductor device packages hinders miniaturization due to loop height issues, is vulnerable to mold flow, and causes parasitic inductance leading to high impedance, affecting package performance.
Innovation Solution
A semiconductor package design incorporating a redistribution layer (RDL) structure with dies and an interconnect structure that electrically connects the dies to the RDL without using wire-bonds, utilizing conductive posts and molding compounds to enhance structural strength and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wire-bonding technique is used for electrical connection, then electrical connectivity between semiconductor devices is achieved, but loop height hinders miniaturization of the semiconductor device package
Solution Approach 1:
The patent extracts and eliminates the wire-bonding technique from the semiconductor package structure. Instead of using external conductive wires that create loop heights, the invention integrates electrical connections directly into the package substrate through conductive vias and trace patterns, removing the problematic wire-bond component entirely
Solution Approach 2:
The patent transitions from three-dimensional wire loops extending above the package surface to a planar two-dimensional connection architecture. Electrical connections are routed through the substrate plane using conductive traces and vias, eliminating the vertical dimension occupied by wire bonds and reducing overall package height
2Reliability
If wire-bonding technique is used, then electrical connection is established, but the conductive wire is vulnerable to mold flow during manufacture
Solution Approach 1:
The patent merges the electrical connection function with the package substrate structure itself. Conductive vias and trace patterns are integrated directly into the substrate, eliminating the need for separate wire-bond components that are vulnerable to mold flow. The connection structure and substrate become a unified, mold-resistant assembly
Solution Approach 2:
The patent performs electrical connections during the substrate fabrication process before molding occurs. Conductive vias and traces are formed in the substrate prior to the molding step, ensuring that connection structures are already protected by the substrate material when molding takes place, preventing mold flow damage to conductive wires
3Reliability
If relatively long wire(s) are used for connection, then electrical connectivity is achieved, but parasitic inductance increases leading to relatively great impedance at high frequencies
Solution Approach 1:
The patent segments the electrical connection path into multiple short sections distributed through the substrate. Instead of using a single long wire, the connection is achieved through a series of short conductive vias and trace segments that collectively provide the necessary electrical connectivity with minimal total length and reduced parasitic inductance
Solution Approach 2:
The patent transitions from long wire connections extending through space to compact planar trace patterns routed through the substrate. Electrical connections are established through two-dimensional trace routing and vertical via connections within the substrate, dramatically reducing the physical length of conductive paths and associated parasitic inductance
Data Source
AI summary
A semiconductor package includes a redistribution layer (RDL) structure, a first die, a molding compound and an interconnect structure. The first die is disposed on the RDL structure. The molding compound is disposed on the RDL structure. The interconnect structure electrically connects the first die to the RDL structure.