RDL Interposer Metal Via Structures for Semiconductor Packaging
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Solution Overview
Problem
The challenge in semiconductor packaging is the high cost and handling difficulties of TSV silicon interposers, which are expensive and prone to warping, leading to misalignment issues and reduced production yield in RDL interposer structures without TSVs.
Innovation Solution
A method for fabricating a semiconductor package using a thin RDL interposer structure involves forming trenches in a substrate, filling them with conductive material to create metal via structures, and forming redistribution layers with metal pillars for connecting semiconductor dies, followed by substrate thinning and wet etching to expose metal pillars for solder bumps, eliminating the need for photolithography and addressing warping issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If TSV silicon interposer is used, then fine pitch interconnections are achieved, but cost increases significantly
Solution Approach 1:
The patent replaces expensive TSV silicon interposers with a cost-effective RDL interposer structure using standard semiconductor fabrication processes. The RDL (redistribution layer) interposer achieves fine pitch interconnections through planar metallization layers rather than through-silicon vias, significantly reducing material and manufacturing costs while maintaining electrical connection quality
Solution Approach 2:
The patent extracts the essential function of the TSV interposer (providing fine pitch interconnections) from its expensive silicon TSV implementation and realizes it through a simplified RDL structure. By removing the TSV complexity and using planar RDL metallization, the solution achieves the same interconnection function at lower cost
2Ease of manufacture
If thin RDL interposer structure is used, then cost is reduced, but warping occurs leading to misalignment
Solution Approach 1:
The patent performs preliminary actions by forming the RDL interposer structure with controlled thickness and mechanical properties before the final packaging steps. The interposer is fabricated with appropriate layer compositions and thicknesses that pre-compensate for potential warping, ensuring alignment accuracy is maintained throughout subsequent processing
Solution Approach 2:
The patent controls warping by adjusting key parameters of the RDL interposer structure including layer thickness, material composition, and metallization patterns. By optimizing these parameters, the interposer maintains dimensional stability and prevents misalignment during packaging while retaining the cost advantages of the thin RDL structure
3Measurement precision
If photolithography is used to define pad openings, then precise patterns are achieved, but warping causes misalignment and reduces yield
Solution Approach 1:
The patent performs preliminary actions by defining pad openings and metallization patterns on the RDL interposer before the interposer is thinned or assembled. By establishing precise patterns early in the fabrication process when the substrate is still rigid and stable, the solution avoids alignment issues that would occur if patterning were attempted after thinning, thereby maintaining both precision and yield
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces production costs, improves alignment accuracy, and enhances production yield by avoiding misalignment due to warping, while enabling fine-pitch interconnections without the use of expensive TSVs.
Implementation Method 1
The remaining portion of the substrate is removed by wet etching to expose the first passivation layer and protrudent portions of the metal via structures, thereby forming second metal pillars
Data Source
AI summary
A method for fabricating a semiconductor package is disclosed. A substrate is provided and a first passivation layer is formed on the substrate. Trenches are formed partially through the substrate. Metal via structures are formed in the trenches. An RDL structure is formed on the first passivation layer. A second passivation layer is formed on the RDL structure. Openings are formed in the second passivation layer to expose bump pads. First metal pillars are formed on the bump pads. Semiconductor dies are mounted onto the metal pillars. A molding compound is formed to cover the semiconductor dies. The substrate is removed, thereby exposing the first passivation layer and protrudent portions (second metal pillars) of the metal via structures. C4 bumps are formed directly on the second metal pillars, respectively.