3D IC Package RDL Interposer TSV Pitch Reduction
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Solution Overview
Problem
Current 3D IC packaging technologies face limitations in reducing the pitch of through semiconductor vias (TSVs) due to lithography constraints, leading to increased area consumption and challenges in aligning interconnects between IC dies, which restricts the number and density of interconnections.
Innovation Solution
The introduction of a redistribution layer (RDL) within an interposer between the IC bottom and top dies, along with under bump metallization (UBM), allows for the routing and fanning out of TSVs to accommodate various micropillar arrangements on the top die, enabling non-aligned interconnect positioning and reducing the overall footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If lithography processing is used to create wiring layers on the back side of the bottom die, then interconnects can be formed, but the line-space dimensions are limited to 8 to 10 micrometers due to warpage preventing high resolution imaging
Solution Approach 1:
A carrier wafer is introduced as an intermediary substrate to support the bottom die during back-side wiring processing. The carrier wafer provides a stable platform that eliminates warpage issues, enabling high-resolution lithography to achieve line-space dimensions of 1 micron or less, thereby resolving the contradiction between manufacturing precision and ease of operation.
2Area of stationary object
If TSV pitch is reduced to decrease footprint area, then area utilization improves, but the number of interconnections that can be mated with top die micropillars is limited by current lithography capability
Solution Approach 1:
The interconnection process is segmented into two independent stages: bottom die TSV formation (optimized for small pitch and area) and top die micropillar formation (optimized for connection density). The carrier wafer enables the bottom die to achieve fine-pitch TSV arrangements without being constrained by top die micropillar spacing, allowing maximum area utilization while maintaining high interconnection counts through the carrier-mediated bonding process.
3Manufacturing precision
If additional wiring layers are formed by re-introducing the wafer with carrier into the fab, then smaller wire dimensions can be achieved, but logistical challenges and contamination risks arise
Solution Approach 1:
The carrier wafer is prepared in advance with all necessary wiring layers and interconnect structures formed before the bottom die is attached. This preliminary action allows high-precision wiring to be created in a controlled environment, eliminating the need to re-introduce the assembly into the fab later and avoiding contamination risks while achieving small wire dimensions.
4Ease of manufacture
If TSV placement pitch is increased to accommodate current micropillar spacing, then fewer TSVs are needed, but larger amounts of valuable wafer area are consumed
Solution Approach 1:
The carrier wafer acts as a mediator that decouples the pitch requirements of bottom die TSVs from top die micropillars. This allows TSVs to be placed at optimal fine pitch for maximum area utilization, while the carrier wafer absorbs the pitch mismatch, enabling flexible arrangement of micropillars on the top die without constraining bottom die TSV density.
Data Source
AI summary
A 3D IC package includes a bottom die having a back interconnect side opposing a front device side, the back interconnect side having a plurality of bottom die interconnects extending thereto. A top die has a front device side opposing a back side, the front device side having a plurality of top die interconnects. An interposer includes a redistribution layer (RDL) between the bottom die and the top die, the RDL including a plurality of wiring layers extending from back side RDL interconnects thereof to front side RDL interconnects thereof. An under bump metallization (UBM) couples the back side RDL interconnects to the plurality of top die interconnects at a first location, and the front side RDL interconnects are coupled to the plurality of bottom die interconnects at a second location. The first location and second location may not overlap.