RDL Metallic Layout Balancing for Substrate Warpage Reduction

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Solution Overview

Problem

The existing redistribution layer structure in semiconductor integrated circuits introduces substrate warpage due to stress, leading to passivation defects and circuit reliability concerns, particularly due to unbalanced orientation and spacing of RDL metallic features.

Innovation Solution

The redistribution layer structure is modified by inserting dummy features and adjusting the layout of RDL metallic features to balance the X-Y ratio gap and reduce spacing, thereby minimizing deformation and stress-induced warpage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the RDL metallic features are arranged with unbalanced orientation and spacing to achieve routing functionality, then the circuit connectivity is improved, but substrate warpage occurs due to stress imbalance

Engineering Contradiction:
Improvecircuit connectivityVSAvoidsubstrate warpage
Core Design Contradiction:
Ease of operationVSStability of the object's composition

Solution Approach 1:

The patent applies local quality by inserting dummy RDL metallic features specifically in regions where stress compensation is needed, rather than uniformly distributing all features. This creates localized stress balance zones that counteract the warpage-causing stress from the functional routing features, while maintaining the required connectivity patterns in critical areas.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent utilizes asymmetry by strategically placing dummy features with different orientations and spacings in different regions of the substrate. The dummy feature distribution is asymmetric relative to the functional features, creating a counterbalancing stress pattern that compensates for the asymmetric stress generated by the routing requirements.

Inventive Principle:
Principle #4Asymmetry

2Area of stationary object

If the RDL metallic features are densely packed to reduce spacing and improve integration, then the device area is reduced, but stress concentration increases causing warpage

Engineering Contradiction:
Improvedevice areaVSAvoidstress concentration
Core Design Contradiction:
Area of stationary objectVSStress or pressure

Solution Approach 1:

The patent segments the RDL metallic features into functional features and dummy features with distinct roles. The dummy features are segmented and distributed in specific patterns to break up stress concentration zones created by dense functional feature packing, thereby reducing overall warpage while maintaining compact device area.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dummy RDL metallic features act as intermediaries between the densely packed functional features and the substrate. These intermediary features distribute and redistribute the stress fields, preventing stress concentration at critical locations and reducing the net warpage effect while allowing dense feature packing.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If the RDL metallic features are oriented primarily in one direction to simplify routing, then the manufacturing complexity is reduced, but unbalanced stress distribution causes substrate deformation

Engineering Contradiction:
Improvemanufacturing complexityVSAvoidsubstrate deformation
Core Design Contradiction:
Device complexityVSShape

Solution Approach 1:

The patent changes the orientation parameter of dummy RDL metallic features to be different from the primary routing direction. By introducing features with varying orientations (including perpendicular and diagonal orientations), the stress distribution parameters are balanced across multiple directions, preventing substrate deformation while keeping the primary routing simple.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240404853A1Redistribution layer metallic layout structure and method with warpage reduction
Publication Date: 2024.12.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240404853A1 patent drawing
  • US20240404853A1 patent drawing
  • US20240404853A1 patent drawing

AI summary

The present disclosure provides a method according to some embodiments. The method includes receiving an integrated circuit (IC) layout of a semiconductor structure that includes a redistribution layout (RDL) structure having a plurality of RDL metallic features; modifying the IC layout such that the modified RDL structure meets a criterion associated with a X-Y ratio gap; generating a tape-out according to the modified IC layout; and fabricating the semiconductor structure according to the modified IC layout defined in the tape-out.